| In this dissertation a new application utilizing error correction code (ECC) decoders is studied, wherein a feedback control loop is attached to the decoder in order to tune the device until it produces a desired average bit error rate (BER) on its codeword estimates. The resulting structure is aptly named a bit error rate locked loop, abbreviated as BERLL. The specific design of the ECC decoder lying at the heart of the loop is not of foremost importance; only the input-to-output characteristics of the decoder and its associated impact on the control loop is considered relevant. The feedback controller takes as input the soft log-likelihood ratio (LLR) variables used by the decoder to determine codeword estimates, while delivering various configuration outputs back to the decoder to achieve the target BER. A trade-off between decoder error correction performance and multiple decoder parameters is thus levied in an effort to minimize the decoder system resource burden while meeting a specified data reliability objective. Direct benefits of operating the decoder in a reduced performance mode include decreased decoder power consumption and decreased decoder throughput latency, per codeword. The loop components of the BERLL are each examined in turn and their impact on overall loop performance is analyzed and discussed. Two independent methods of controlling the performance of the ECC decoder are examined with mathematical analysis and software simulation of the closed loop time domain and frequency domain responses. |
