| This dissertation presents a new architecture for scheduling threads to processors and handling I/O. The architecture combines many of the useful features found in kernel-level and user-level threads into a single thread model. From the kernel-level thread, these features include the ability to context-switch to hide most events that would prevent good processor utilization such as resuming a preempted thread. From the user-level thread, these features include the ability to context-switch or resume a preempted thread without the need to make a system call. This new thread is referred to as a nanoThread, and it is scheduled out of a run queue shared by the operating system and a user-level scheduler. The essential context for a thread is stored within the shared arena. Whether the operating system or the user-level scheduler suspends a thread, it is feasible for either scheduler to resume the suspended thread. The user-level facility to schedule the same threads as the operating system also impacts the design of other, common user-level runtime functionalities like synchronization. These portions of the user-level runtime are modified to operate safely and take advantage of having operating system preemption information in the shared arena.; The impacts of a shared arena architecture for scheduling threads is analyzed with legacy applications such as FORTRAN computational chemical simulations and mathematical solvers that consume significant processing time in large systems and are difficult to redesign. A representative set of applications from the NAS benchmarks had only their runtime replaced with a new runtime that makes use of the shared arena in IRIX 6.5, and were found to improve their execution time over 14 times when there was a single process used in a 16 processor Origin 2000 from Silicon Graphics, Inc. Another implementation in Linux 2.4 was used to test context-switch performance amongst comparable thread models. Though, the nanoThread scheduler interface is more complicated than the comparable threading designs presented, the performance improvements shown in this dissertation prove that this more efficient thread model warrants implementation in commercial operating systems. |
