| Shared-memory multiprocessors are gaining wide acceptability since they are easy to program. Cache-coherent non-uniform memory access (CC-NUMA) architectures provide a scalable design for shared memory multiprocessors. This dissertation is focused on the following issues related to CC-NUMA architectures: (1) Design, analysis, and evaluation of static memory management policies for CC-NUMA multiprocessors that try to allocate shared data in the local memory and avoid remote memory accesses; (2) Design, analysis, and evaluation of switches that provide caching of remote data in interconnection networks; (3) Design, analysis, and evaluation of CC-NUMA multiprocessor architectures for internet protocol (IP) router application.; Memory management plays an important role in CC-NUMA multiprocessors since it governs the placement of shared data. Here, two improved static memory management policies are developed and their performance is compared against a spectrum of the existing static memory management schemes. In order to investigate the performance impact of existing and improved memory management policies accurately, we employ an execution-driven simulation methodology, which models the interconnection network and switch architectures in detail. Sensitivity studies related to both memory management and network design are presented.; Interconnection network is a crucial component of CC-NUMA architectures. Switches are basic building blocks for interconnecting CC-NUMA multiprocessors. Switch design has significant effects on the system performance. We develop two new switches, called switch MSHR (SMSHR) and switch MSHR+cache (SMSHR+cache), to improve the memory system performance of CC-NUMA architectures. To illustrate the performance of the new switches, we implement them in a simulator and compare the results with those from several existing techniques in detail.; Here, another important aspect of this work is designing and evaluating a CC-NUMA multiprocessor architecture for IP routers. A methodology is proposed which incorporates an IP router in an execution-driven simulator. We develop a technique to feed the simulator with real internet traces so that the property of real internet packets can be studied and incorporated into the simulation process. We present different design alternatives for IP routers. With the results of our simulation experiments, we analyze the performance of IP routers at the system level and the switch fabric level. |
