| Code compression is proposed as a solution to the code size problem for embedded systems. Data compression techniques are used to compress programs to reduce memory size. The compressed programs are then decompressed on-the-fly during execution. However, decompression overhead may induce performance deterioration; therefore, fast decompression schemes and decompression architecture designs are very important when designing a good code compression scheme.; In this dissertation, we provide a suite of code compression techniques as well as decompression architecture designs for embedded systems. The FV2CC (Fixed-to-Variable Code Compression) uses fixed-to-variable coding schemes based on a reduced precision arithmetic coding. Multi-bit parallel decompression architecture designs for FV2CC are presented. The V2FCC (Variable-to-Fixed Code Compression) uses variable-to-fixed coding schemes based on Tunstall coding and arithmetic coding algorithms. The techniques are suitable for both RISC architectures and VLIW architectures. However, since code compression for VLIW architectures are not well studied as RISC architectures, we mainly apply the techniques on VLIW architectures. Code density is not the only design goal for embedded system. In this dissertation, we also propose a profile-driven code compression methodology. By using execution profiling, we can achieve instruction bus power reduction via instruction re-encoding, or selectively compress infrequently used instructions such that the performance of a processor is not compromised too much due to the decompression overhead.; In summary, the contributions of this dissertation include code compression algorithms and decompression architecture designs which balance the compression ratio and decompression overhead, instruction bus encoding techniques that reduce the bus power consumption, and a profile-driven code compression methodology that balances the compression ratio and processor performance. We use VLIW architectures as the target embedded architectures, however, the techniques are general and suitable for RISC architectures as well. (Abstract shortened by UMI.)... |
