Algebraic Code Algorithms In Finite Fields And Their VLSI Architectures

Algebraic error-correcting codes in finite fields are widely applied in Ethernet,optical network communication,and large capacity storage.The next generation of Ethernet and optical network communication needs a more high-speed and reliable communication transmission scheme,while the next generation of large-capacity storage technology needs ultra-low latency and ultra-low power consumption error-correcting scheme.The core research directions of these technical schemes all involve the selection of forward error correction code(FEC)scheme and the design of VLSI hardware architecture.Meanwhile,the power consumption of decoder can be reduced as much as possible,while required throughput could be guaranteed.For a single error-correcting code,the net coding gain can be improved by increasing the code length.However,with the increase of code length,decoding complexity and decoding delay of the decoder will also increase dramatically.In order to solve the contradiction between performance and computational complexity,combinatorial algebraic codes such as concatenated codes and product codes are generally adopted to ensure the length of long codes without making the decoding complexity and latency unbearable.This paper mainly studies the decoding algorithm of combinatorial algebraic code error correction scheme and its corresponding VLSI hardware architecture.The component codes of combinational algebraic codes,in this paper,are BCH and RS codes.We focus on the low complexity decoding algorithm of RS and BCH codes and the corresponding VLSI architecture design with high throughput and low latency.Then,the improved algorithm and efficient architecture of BCH and RS codes are applied to various combinational algebraic codec schemes,such as concatenated codes and product codes.In this paper,a concatenated codes decoder with throughput over 200 Gb/s,power consumption less than 200 mW and delay less than 127 ns is implemented.Furthermore,the concatenated codes are extended to the codec scheme of generalized concatenated codes(GCC).Compared with concatenated codes,GCC can further reduce the code-length of component codes so as to reduce the decoding latency.In addition,the theoretical curve of GCC is in good agreement with the Monte-Carlo simulation in C language,which proves that the proposed decoding scheme has good theoretical predictability.In order to make the theoretical calculation more convincing,a RTL simulation verification is implemented on the xcvu440-fpga2892-1-c type of FPGA.The BER curve of GCC is simulated to the magnitude of 1 × 10-15.At such a low BER,the validation results still agree with the theoretical results.Finally,the RTL of GCC decoder is synthesized by the Synopsys DC,which achieves throughput over 200 Gb/s and decreases decoding delay greatly compared with the concatenated code.At the same time,the power consumption of the decoder is also reduced.