New dynamic power supply current testing methodologies for very deep sub-micron CMOS circuits

In this dissertation, we investigate the new types of defects that emerge in very deep sub-micron (VDSM) technologies and that cannot be detected using the existing fault models and the available testing techniques. We propose two new testing methods that can be used with VDSM CMOS circuits, mainly for detecting resistive defects such as resistive opens and resistive bridges. We refer to these methods as Double Threshold method and Delayed i_DDT method respectively. Both methods are based on monitoring and analyzing the dynamic power supply current, i_DDT. We develop and implement in software an algorithm that automates the process of generating test vectors for the proposed testing methods. We evaluate the effectiveness of the ATPG tool and the testing methods with benchmark circuits such as the ISCAS circuits. Finally, we propose a clustering technique that can improve the fault coverage of the Double Threshold method. We develop and implement in software an algorithm that automates this process of circuit partitioning and we verify the improvement it provides using the ISCAS benchmark circuits.