On the sliding-window packet-switching architecture for large-scale internet routers and switches

The partition of a system into parallel elements to scale the system in size and capacity is widely used by the research community. The idea to divide a large and central memory in shared-memory-based switching systems into an array of parallel memory modules to reduce the memory-bandwidth requirements seems like a reasonable idea. However, scaling a shared-memory-based switching system has becomes an extremely challenging task that the research community has focused in other approaches to build high-speed and large-size Internet router and switches. In this dissertation, the sliding-window (SW) packet-switching architecture is presented as a truly scalable shared-memory-based switching system.;The SW packet-switching architecture is not a new idea. The SW packet-switching architecture is a novel approach that combines the memory utilization of a shared-memory switch and the parallel operation of the memory modules in an input-queued switch. This dissertation shows how to achieve the potential of the SW packet-switching architecture with algorithms that have linear complexity as the SW switching system is scaled in size. In this dissertation, algorithms for the SW packet-switching architecture are elaborated and evaluated. Previously unaddressed topics such as the memory efficiency and the effects of varying the window size are investigated. One of the main results is that the window size can be expanded to obtain better performance of the SW packet-switching architecture by having more memory modules in parallel and/or a larger speedup factor in the memory modules. Also, the SW packet-switching architecture is modified in this dissertation to support priority switching for various traffic classes and multicasting to handle point-to-multipoint communications.