Constructions, Analyses and Decoding Algorithms of LDPC codes and Error Control Codes for Flash Coding

The fundamental problem in communication or storage systems is that of reproducing a message at another location or another time with high reliability. Channel codes or error control codes are the key techniques to guarantee reliable information transmission and storage. In the past six decades, many researchers dedicated themselves to design highly efficient error control codes.;Low-density parity-check (LDPC) codes form a class of capacity-achievable codes with powerful soft-decision decoding algorithms. These decoding algorithms have linear complexity. Thus, many LDPC codes have been chosen as the standard codes for various next generations of communication systems and their applications to digital data storage systems are now being seriously considered and investigated. LDPC codes and efficient algorithms for decoding them form the most attractive topic in coding theory in the past 15 years.;Two desirable structures for efficient hardware implementation of encoding and decoding of LDPC codes are cyclic and quasi-cyclic structures. In this dissertation, a new class of cyclic and a new class of quasi-cyclic LDPC codes are constructed by circulant decomposition. The new construction of cyclic LDPC codes enlarges the repertoire of cyclic codes constructed from finite geometries in 2000.;Also presented in this dissertation are two simple but efficient novel reliability-based iterative decoding algorithms of LDPC codes. Both algorithms are devised based on the simple concepts of the one-step-majority-logic decoding algorithm. They provide efficient trade-offs between performance and decoding complexity. These two algorithms can be implemented in a single decoder with dual mode.;In this dissertation, we also investigate application of error control codes to flash memories to reduce block erasures. Flash memories are the most promising devices to replace hard disk drives. However, block erasures are the most challenge problem for the life time of flash memories. Such operations are not only time-consuming, but also cause physical degradation and reduce the longevity of flash memories. A new efficient approach based on error control codes is proposed to reduce the frequency of block erasures.