| The continuous scaling of CMOS technology has fostered a fast increase of integrated circuit speed. However, on-chip global interconnects, especially clock distribution and global bus structures, have exhibited increased delay as technology progresses mainly due to the continuous increase in chip area. These global interconnects are therefore considered to be potential bottlenecks in the design of future high-speed systems. Accurate modeling of these interconnects are greatly needed.; In high-performance IC design, critical global nets, such as the clock network, power distribution, and data bus structures, typically use large dimension top-level interconnects to reduce line resistance. As a result of the increases in clock frequency and reduction of line resistance, inductance effects have become a first-order issue for highly optimized global nets, and simple RC models have become inadequate for simulation of state-of-the-art VLSI circuits. Besides inductance, another electromagnetic effect that emerges at high frequencies is current crowding, which means currents tend to concentrate along line edges and in smaller return loops due to the interaction of electric and magnetic fields. These effects lead to significant frequency-dependent resistance and inductance at high frequencies. In this work, the impact of high-frequency effects on VLSI interconnect behavior is investigated and solutions in terms of modeling and design optimization are proposed. First the effects of inductance on global interconnect signal integrity analysis are studied using full-wave RLC extraction and SPICE simulation. Then analytical models are developed, including RLC parasitics extraction and gate-stage performance. These two models create a direct link from interconnect geometry to performance, which enables fast timing analysis and interconnect physical structure optimization. Examples of the interconnect optimization study are presented and design guidelines proposed for fully-shielded global clock structures. Besides the high-frequency inductance effect on signal and clock nets, parasitic inductance in power distribution networks is studied and a novel circuit design technique to suppress the Ldi/dt noise due to inductance is proposed. |
