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Efficient on-chip inductance modeling

Posted on:2006-09-09Degree:Ph.DType:Thesis
University:University of California, Santa CruzCandidate:Ji, HaoFull Text:PDF
GTID:2452390008976006Subject:Engineering
Abstract/Summary:
On-chip inductance extraction and analysis is becoming increasing critical. Inductance extraction can be difficult, cumbersome and impractical on large designs as inductance depends on the current return path---which is typically unknown prior to extracting and simulating the circuit model.; In this thesis, we propose a new circuit element, partial reluctance K, to model inductance effects, at the same time being easier to extract and analyze. Partial reluctance is defined as inverse of partial inductance, and has locality and sparsity normally associated with a capacitance matrix. Based on the physical interpretation, we explain why the distant partial mutual reluctance can be ignored (locality) and prove that after ignoring distant partial mutual reluctance, the resultant sparse partial reluctance matrix obtained from K-based method is positive definite (stability). To capture more magnetic couplings while preserving symmetry of partial reluctance matrix, we also proposed blocked K method using group concept.; Together with an RKC equivalent circuit model, the locality and stability enables us to simulate RKC circuit directly and efficiently for real circuits. A new circuit simulation tool, KSim, has been developed by incorporating the new circuit element K into Berkeley SPICE. Therefore, we propose to capture inductance effects by directly extracting and simulating partial reluctance, instead of partial inductance, leading to a much more efficient procedure which is amenable to full chip extraction. The RKC simulation matches better with the full partial inductance matrix simulation with significant less computing time and memory usage, compared to other methods.; In case modification of conventional SPICE simulator is not preferred, we have also derived two SPICE compatible circuit models for partial reluctance solely based on transformation of circuit equations. One is voltage controlled voltage source (VCVS) model, the other is current controlled current source (CCCS) model. Both models are as stable, sparse, and as accurate as the K-based method. In fact, they are both mathematically equivalent to partial reluctance K. They can be combined with any partial reluctance based extraction method to perform SPICE compatible RLC simulation with minimum extra elements and no coupling increase. Both mathematical analysis and experiment results demonstrate that the combination of VCVS model and blocked K method achieves the best compromise between accuracy and performance among all SPICE compatible sparsification techniques.
Keywords/Search Tags:Inductance, Model, SPICE compatible, Partial reluctance, Method, Circuit, Extraction
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