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Development of a giga-bit-per-second superconducting serial-to-parallel converter for use in switching and demultiplexing applications

Posted on:2003-08-05Degree:Ph.DType:Dissertation
University:University of Colorado at BoulderCandidate:Vichot, Paul AndreFull Text:PDF
GTID:1462390011484194Subject:Engineering
Abstract/Summary:
This work details the development of a 4-stage serial-to-parallel converter (SPC) based on low temperature superconducting integrated circuit technology. First, the motivation for such a circuit in large data throughput switching and demultiplexing applications is discussed. The theory is then developed for understanding the concepts necessary in the operation and design of the fundamental devices and gates. The computer-aided design tools used for optimizing the circuit designs and predicting their performance are then detailed, with specific attention given to the optimization algorithm.; The design of the SPC is then examined, detailing the evolution from the original circuit design through two revisions. In this development, the metric used for gauging the improvement in performance of the circuit was overall circuit yield and the approach was to broaden the operating margins of the most problematic gates and subcircuits. Details of the fabrication technology and the layout strategy for the circuit designs are then conveyed.; A high-speed cryogenic testing facility was built at the Applied Physics Laboratory and details are given concerning the proper operation of the special purpose MCM probe, flow cryostat and control electronics. The MCM probe and chip carriers are characterized at high frequencies using network analysis and the limitations of this system in terms of both frequency response and package resonances are quantified. Methods for testing the final circuit designs and their constituents at both low and high speeds are developed. A detailed analysis of the high-speed testing system's noise limits is also given.; The low and high-speed testing results for the individual gates and subcircuits are then discussed and the discrepancies between the designed and measured circuit values are quantified. The high-speed testing results for the final circuit design are given with successful operation demonstrated for data rates up to 1 Gbps.
Keywords/Search Tags:Circuit, Development, Testing, Given
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