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Development of an FPGA-based architecture enabling the hardware implementation of a three-dimensional finite -difference time -domain algorithm for the analysis of electromagnetic propagation

Posted on:2005-07-08Degree:Ph.DType:Dissertation
University:University of DelawareCandidate:Durbano, James PhilipFull Text:PDF
GTID:1458390011451483Subject:Engineering
Abstract/Summary:
Although FDTD methods are accurate and well defined, current computer-system technology limits the speed at which these operations can be performed. Run times on the order of hours, weeks, months, or longer are common when solving problems of realistic size. Some problems are even too large to be effectively solved, due to practical time and memory constraints. The slow nature of the algorithm primarily results from the nested for-loops that are required to iterate over the three spatial dimensions and time.;To shorten the computational time of this and other numerical techniques, people acquire faster computers, lease time on supercomputers, or build clusters of computers to gain a parallel processing speedup. These solutions can be prohibitively expensive and frequently impractical. As a result, an approach that increases the speed of the FDTD method in a relatively inexpensive and practical way is required.;To this end, I have developed an FPGA-based acceleration architecture for the FDTD method. The acceleration hardware can accommodate larger problems than PCs and can solve them orders of magnitude faster. This system represents a new era in computational electromagnetic simulations, greatly increasing the speed at which current problems can be solved and permitting the analysis of new designs.
Keywords/Search Tags:Time, FDTD, Speed
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