| While the practice of design reuse is well established for digital circuits, it is not easily applied to analog circuits. One problem is that design constraints of analog circuits are sometimes implicit, which makes porting the design to a new environment difficult and prone to failure. This dissertation describes STAR (Schematic Tool for Analog Reuse), a system that captures designer's knowledge as part of the circuit representation, and then describes how to use this system to create portable design modules.; Creating portable analog modules requires the system to capture not only the sized schematic of the circuit but also the objectives that the circuit is trying to achieve. It must also include the constraints on the cell's environment, and how these constraints should scale with technology. Furthermore, the system should help the designer in the current task of creating the design, since it is rare that a designer thinks about creating IP for someone else.; Our solution captures the design knowledge by enabling the designers to annotate their schematics with special comments, called Active Comments. The designers embed predefined functions in the Active Comments to specify the goals and constraints of the circuits. An execution engine turns these comments into simulation runs to measure the circuit parameters and monitors to check the circuit's operating conditions. There are two types of active comments. One ensures the design meets the specifications, given some constraints on the operating conditions. The other checks that these constraints are satisfied for each instance of the circuit. Using the circuit's intrinsic properties to specify the constraints help make the comment portable.; We demonstrate the capability and utility of this system by examining the reuse of a phase-locked loop (PLL). Using the design knowledge captured in STAR, the PLL is ported to a different process technology and re-optimized. The loop dynamics of the resulting PLL track the operating frequency, with the damping factor varying less than 12% across the frequency range of 500MHz to 1.2GHz. The framework also identified all the potential issues and verified the functionalities of the modified PLL without requiring any expertise of the designer. |
