| Designers of multicore architectures provide many options for bundling resources in the chip package. Simple architectures put multiple cores on a single chip to share bus interfaces and/or a common caches. System-on-a-Chip (SoC) and System-in-a-Package (SiP) designers choose to integrate additional functionality (e.g., audio and video, encryption engines, analog-to-digital converts, etc.) into the single chip package. As the communication complexity increases between different resources in a chip package, multicore designers continue to look at new methods to increase parallelism and scalability. The Network-on-a-Chip (NoC) method attempts to solve these problems by emulating a modern telecommunications network in a single chip package.;As with any new innovation, security architects and analysis must review the security ramifications of multicore architectures. For example, what new communication channels are present in the multicore architecture and what safeguards are available to protect those communication channels? It is not readily apparent that existing multicore architectures maintain proper information flow isolation so as to enable an implementation of secure systems; but single-core information flow identification and evaluation methods do not scale well to modern multicore architectures. This dissertation presents an information flow security analysis of multicore architectures. This dissertation applies the framework to the Cell Broadband Engine Architecture, Freescale P4080, and the Intel i7 Nehalem.;Analyzing the information flow security attributes of multicore architectures is not as simple as conducting multiple single-core analyses, due to the fact that most multicore architectures have onboard virtual systems interfacing the application layer with the SoC. An analysis framework, tailored to the complexities of multicore architectures and their onboard virtual machines, is needed. The framework should expose overt and covert channel vulnerabilities in multicore architectures. |
