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Architecture and design of a CMOS IC for packet switching multi-gigabit data streams

Posted on:2006-12-24Degree:Ph.DType:Dissertation
University:University of DelawareCandidate:Ekman, JeremyFull Text:PDF
GTID:1458390008967825Subject:Engineering
Abstract/Summary:
Communication requirements in high-performance computing systems continue to increase as the processing nodes within these systems grow in capacity. The work described here looks to future solutions to increasing network bandwidth while maintaining scalability within physically constrained systems by using free-space optical links to implement high-density chip-to-chip interconnection. Such links have advantages over their electrical counterparts in their ability to provide reliable, high-performance connectivity within areas of dense signal routing.; In order to address scaled interconnection bandwidth requirements within switched networks, a system design is presented that consists of a custom switch design that uses wide free-space optical channels between multiple integrated circuits on a multi-chip module to form a scalable switch fabric. In order to show the feasibility of such a system, a hardware demonstration based on custom electronics was built and tested. This included a silicon-CMOS chip that was hybridized with a monolithically integrated array of vertical-cavity surface-emitting lasers and photodetectors that implemented the interconnectivity utilized by the switch design. The resulting hardware demonstrated simultaneous optical communication between seven hybrid chips and is unique in the large scale use of free-space optical interconnects based on this technology. The switch architecture will be presented along with the hardware implementation and system test results.
Keywords/Search Tags:Switch, System
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