Design-technology co-optimization in next generation lithography

Lithography continues to be the backbone of the integrated circuit (IC) industry. While the critical dimension (CD) keeps shrinking with the pace of Moore's law, the progress in lithography lags far behind. The gap between manufacturing capability and the expectation of design performance finally pushes the conventional 193 nm ArF immersion lithography to its limit, calling for a complete new set of design and manufacturing methodologies under the scope of next generation lithography. Many innovations are needed to co-optimize both design and process at the same time. Design-technology co-optimization (DTCO) in next generation lithography (NGL) could be defined very differently under different circumstances. In general, progress in NGL happens along four different directions: · new patterning technique (e.g. litho-etch-litho-etch, self-aligned pattering), · new design methodology (e.g. restricted design rule, 1-D design), · new illumination system (e.g. extreme ultraviolet lithography, electronbeam, directed self-assembly), · new simulation and verification approach (e.g. process windows optical proximity correction, parallel simulation).;Corresponding to these four research directions, in this dissertation, we propose our research topics as follows: · Self-aligned double patterning (SADP)/self-aligned quadruple patterning (SAQP) for new patterning technique (Chapter 2 -- 5), · 1D design for new design methodology (Chapter 6 -- 8), · Extreme ultraviolet (EUV) for new illumination system (Chapter 9 -- 10), · Graphics processing unit (GPU)-based aerial image for new simulation method (Chapter 11).;For the research direction of new patterning technique, we mainly study self-aligned patterning techniques. SADP process has been studied extensively in the past. This self-aligned type double patterning strategy is designed to mitigate the inevitable overlay in other pitch-splitting multiple patterning techniques, such as litho-etch-litho-etch (LELE). However, SADP-based design-technology flows are still incomplete in three senses. First, in SADP process the mask pattern is no longer the designed pattern, which necessitates an efficient decomposition approach for mask generation. Second, how to find a decomposition result which has the best overlay control is a non-trivial question. Third, design rule check should be largely expanded to detect the hot spot in the layout which makes the whole layout indecomposable. In this dissertation, we propose a flow for SADP decomposition, which takes all the above incompleteness into consideration. This study leads to the first published decomposition algorithm, the first overlay minimization algorithm and the first hot spot detection algorithm for SADP decomposition. As an extension, we then propose a novel characterization flow to provide the first design enablement estimation method for SAQP lithography.;For the research direction of new design methodology, our major contribution is on 1D design optimization. 1-D regular design style is a novel design style under the requirement of restricted design rule for better process windows. By different pitch requirements under different technology nodes, 1-D circuit patterns can be manufactured by single patterning or print-and-cut technique. For the single patterning technology, we study tip-tip gap distribution for a better process window and propose a novel algorithm to retarget the line-ends and floating dummies with/without performance impact constrains. With our proposed algorithms, we can significantly increase the process windows with limited impact on the original design. For the print-and-cut technique, we focus on the mask cut complexity reduction. By optimally extending the line-end, we can largely reduce the cut mask complexity and thus save manufacturing costs.;For the EUV process as a new illumination system, we focus on a defect mitigation algorithm. EUV process is a new process compared to the conventional 193 nm immersion lithography. With only 13.5 nm wavelength, EUV process has a capability to work on the circuit in sub-20 nm technology node. However, before the final implementation of EUV process, defective blank for mask manufacturing is still a huge problem that needs to be addressed. In this dissertation, we propose an efficient layout shift and rotation method to mitigate blank defect impact. Our algorithm shows a significant speedup compared to the existing commercial tool. We also update our algorithm to further accept the small angle rotation movement to increase the success rate of defect mitigation.;For the new simulation/verfication method research direction, we utilize GPU to achieve a substantial contribution to aerial image simulation. Aerial image simulation is a fundamental step in the process-related simulation and verification, which requires vast numerical computation. The recent advancement of general purpose GPU computing provides an excellent opportunity to parallelize the aerial image simulation and achieve great speedup. In this dissertation, we present and discuss two GPU-based aerial image simulation algorithms. Compared to the previous work, our approach has significant speedup and much smaller numerical errors.