| Space-time processing has been gaining increasing attention from both academia and industry in recent years. However, most of the research till now remains limited to the theoretical aspects and many practical issues for implementation are still untouched. This dissertation presents the VLSI implementation of a highly flexible, dynamic reconfigurable, RLS algorithm based MIMO detection engine, which is capable of broadband MIMO-OFDM transmissions with up to 8 transmitters and 8 receivers.; The major challenge facing the implementation of MIMO detection is the high computational complexity of space-time processing algorithms. Various linear and nonlinear MIMO detection algorithms have been identified and compared in terms of performance and implementation cost. Among them, RLS algorithm converges to MMSE performance through a series of iterations and requires one order of magnitude lower complexity than ZF/MMSE algorithms. On the other hand, its speed of convergence is much faster than LMS algorithm. Therefore, it has been chosen to be implemented in the ASIC.; Despite the lower complexity, RLS algorithm is usually known to be numerically unstable. The square root forms of RLS algorithm that are based on QR decomposition have been developed previously to solve this problem in the scenario of beamforming and equalization. Here, all three different forms of QR-RLS have been adapted to the MIMO detection. They are then mapped to systolic array architectures, which handles the matrix computations such as triangularization and multiplications through a regular and easily scalable structure. Among the three, inverse QR-RLS requires the smallest array and has been picked as the architecture to be committed to silicon. To ensure the stability, the internal dynamic range of the inverse QR-RLS systolic array has been estimated through simulations and the result is used to determine the finite word length of internal signals. These word lengths are further optimized using finite precision simulations.; The MIMO detection engine has been fabricated using TSMC 0.18mum CMOS technology. The device incorporates a special input labeling mechanism that enables adaptation to different packet structures. Each array cell processes its inputs only based on associated label, and it's not necessary for it to know its location in the array explicitly. (Abstract shortened by UMI.)... |
