Circuit techniques for low-latency, low-energy intrachip communications

Technology scaling over the past few decades, which has more or less obeyed Moore's law, has led to ever-increasing transistor speeds and densities (transistors/mm2). Aggressive scaling has resulted in modern-day microprocessors with millions of transistors with an enormous amount of computing power. This has nonetheless come at the expense of increased design complexity and higher power dissipation. Such high performance processors call for a high-speed on-chip data communication network to exploit the core processor speed - bottlenecks in this on-chip data network will result in wasted CPU cycles. Conventional on-chip interconnects (e.g. optimally buffered links) are too slow to keep up with increasing global clock frequencies. Latencies of these conventional links have gone up from a negligible fraction of the clock period to a few clock periods in today's cutting edge processors. This latency problem is in addition to their increasing power consumption, which goes up linearly with frequency (Power ∝ f.C.V 2).; This work investigates two different architectures for low-latency on-chip links for global communication. Both of them exploit the transmission line behavior of interconnects at high enough frequencies to achieve low latencies. The first technique uses sharp current pulses to modulate transmitted energy and enhance the high frequency components in order to exploit the increased phase velocities at higher frequencies. The higher phase velocity comes at the expense of increased attenuation. The absence of repeaters in this implementation further lowers the overall latency resulting in on-chip links with near speed-of-light latencies. However, the increased attenuation at higher frequencies along with the lack of repeaters restricts the maximum length of these on-chip links. The second technique that was investigated uses distributed loss compensation using negative impedance elements to achieve both low latencies and lower power consumption. This technique, which has been employed in distributed amplifiers and oscillators, compensates for signal attenuation along the line using negative impedance elements allowing for low-swing transmission line operation up to arbitrary line lengths.; Two prototype chips in 0.18mum CMOS technology were fabricated to study the effectiveness of both these techniques. Measured latencies of 6.5 ps/mm were achieved at a throughput of 8 Gb/s for the pulsed current-mode signaling scheme over a 3 mm link. The distributed loss compensation approach resulted in a latency of 12.1 ps/mm at a throughput of 3 Gb/s over a 14 mm long interconnect. This compares with a latency of more than 18.6 ps/mm for conventional optimally repeated links. The latter approach also resulted in a 3X reduction in the overall power consumption when compared to optimally repeated links while the pulsed current-mode signaling scheme resulted in a 3X increase in power consumed when compared to the same technique.