Sampled charge reuse for power reduction in switched capacitor data converters

Advances in semiconductor fabrication have enabled the shrinking of digital systems dramatically over the years. Although digital circuitry benefits tremendously from the constant shrinking of the device sizes, the benefits for analog circuits are not quite so dramatic. Low power is of critical importance in all mobile devices. Any reduction in power in the embedded analog-to-digital converters (ADCs) in such devices can help prolong the battery life. A technique is proposed that can be used to reduce power dissipation in ADCs that use switched-capacitor gain stages. It is shown for a pipeline ADC that the signal charge stored across the feedback capacitor from the first stage can be reused in the second stage at the end of the first stage's amplify phase. The extra overhead of an extra capacitor is justified by the power savings of the proposed scheme.; A well known approach for reducing the power dissipation in pipelined ADCs is the scaling down of capacitors progressively down the pipeline stream. The proposed technique combines the scaling of the capacitors with charge reuse. This combination inherits the power saving benefits of capacitor scaling and adds to the power saving by sharing the capacitor in two consecutive stages. Due to the highest power budget allocated to the first two stages, the sharing 2 is limited to the first two stages. Additionally, it is shown that the charge reuse results in reducing the total capacitive load driven by a stage's opamp, potentially reducing the current requirements of the opamp.; The proposed technique has been adapted for use in cyclic ADCs. The proposed technique reuses the charge from the first cycle in the next. This approach helps to reduce the die area of the capacitors in the switched capacitor network by up to 50%. Consequently, the power consumption requirement of the operational amplifier can be reduced. This is achieved while maintaining the thermal noise performance and conversion rate of the conventional structure. A 10-bit, 2.3MHz cyclic ADC using the new structure is implemented in 0.5mum CMOS. Spectre simulation results show a THD of -76dB and SFDR of -74.95dB.