A NMOS LDO Without Off-Chip Capacitor

With the rapid development of integrated circuits,5G communication,the Internet of things,new energy vehicles and mobile terminal equipment and other scientific and technological products come out,the role of power management chips in the system is getting more and more attention,and high-performance power management chips are constantly bringing forth the new.In many power management chips,LDO linear regulators rely on the advantages of simple structure,stable output voltage,low noise,small ripple,low overall cost and is widely integrated in analog and RADIO frequency chips as the power supply for each module,and gradually to So C chip system integration.Without external compensation capacitors or small capacitors to save chip area and reduce the overall cost,LDO without external capacitors has become a hot research topic.This thesis r introduces the basic working principle of the traditional LDO linear regulator,studies and analyzes the function of its off-chip compensation capacitor,and compares the principle of the LDO linear regulator with or without external output capacitor.Circuit principle and topology of NMOS LDO without off-chip capacitors.The working principle of the NMOS LDO without off-chip capacitors designed in this paper is introduced,and the circuit principle and simulation results of the circuit neutron module are introduced and analyzed.In this design,NMOS is used as the power tube of the LDO,the folded cascode amplifier is the error amplifier of the LDO,and the charge pump is the topology of the boost circuit.In this design,the charge pump adopts a new type of cross-coupling structure,which can effectively reduce the output ripple and improve the driving capability of the charge pump to a certain extent.This design is stable without the need for an off-chip output capacitor.And joined the overtemperature protection,over-current protection module to ensure the normal operation of the LDO.Through the overall circuit design,the adjustable output voltage of 1.2-5V is realized,and the simulation verification and analysis are carried out,and the layout design of the chip is completed.This design is based on Hua Honghong’s BCD350 nm process design chip,and uses Cadence’s EDA tool to carry out DC simulation,AC simulation and transient simulation of the circuit in this paper.Through simulation,it is found that when the input voltage is in the range of 1.7-5.5V,by adjusting the resistance of the feedback network resistor,a stable output voltage in the range of 1.2-5V can be achieved,with a wide range of 1μA-400 m A load capacity;typical voltage drop The voltage value is about 82 m V;the linear regulation rate is 0.00684%/V when the（light load）load current is 1μA,and the linear regulation rate is 0.00815%/V when the（heavy load）load current is 400 m A;when the load current is 1μA-400 m A The load regulation rate is 0.00850%/A within the range of variation of is 198 m V;undershoot settling time is 1.27μs.And in the temperature range of-40℃-125℃,the output is stable.The simulation results show that the LDO designed in this paper meets the design requirements.Compared with similar published research results,the LDO designed in this paper has obvious advantages in output load current.