Modeling quantum and Coulomb effects in nanoscale devices

The impact of quantum-mechanical size-quantization and Coulomb: discrete dopant effects on the operation of nanoscale metal-insulator-field-effect-transistor (MOSFET) device structures has been investigated using classical three-dimensional (3D) Monte Carlo particle-based simulator. Quantum confinement is treated via two different effective potential formalisms: (1) Ferry's effective potential scheme that takes into account the natural non-zero size of an electron wave packet in the quantized system. When employed in the simulations of narrow-width silicon-on-insulator (SOI) device structures, it is found that the two-dimensional (2D) carrier confinement in the active region results not only in a significant increase in the threshold voltage (∼180 mV for a device with 10 nm channel width, which gives rise to 15--25% on-state current reduction) but also in its pronounced channel width dependency and thus explaining the experimentally observed quantum mechanical narrow-channel effect. (2) A novel parameter-free quantum field scheme for use in conjunction with Monte Carlo particle-based simulations, which is based on a perturbation theory around thermodynamic equilibrium and leads to a quantum field formalism in which the size of the electron depends upon its energy. The approach has been tested on the example of a MOS-capacitor by retrieving the correct sheet electron density. It has also been used in the simulations of 25 nm and 15 nm n-channel MOSFETs that require very high substrate doping to prevent the punch-through effect which, on the other hand, leads to pronounced quantum mechanical space-quantization effects. The quantum field approach is found to produce the experimentally extracted threshold voltage shifts of about 200--220 mV and leads to drain current degradation of about 15--30%. To further test the applicability, the quantum field formalism is used to calculate the threshold voltage and output characteristics of recently proposed single-gated (SG) and dual-gated (DG) fully-depleted silicon-on-insulator (FDSOI) devices. It is observed that the method quite correctly retrieves the trend in the threshold voltage shift with the variation of active layer silicon film thickness. The simulation results are verified with the available experimental and/or theoretical data. (Abstract shortened by UMI.)...