| The design and test of integrated circuits faces a new set of challenges as mainstream production continues to move into deep-submicron process technologies. Fixed delay, deterministic models and methodologies are losing steam against the uncertainty caused by process variation and unmodeled effects. This dissertation presents several statistical methods for enhancing the value of delay testing in this environment. First, a fast statistical timing simulator is developed to estimate the statistical timing behavior of test patterns. This information can the be used to optimize the selection of delay test patterns. Next, this dissertation advocates a change of perspective for delay test with the concept of parametric delay test. If delay test is viewed more as a measurement, this enables a rich suite of post-silicon analysis and optimization opportunities. We present several methods in which statistical learning can enable this analysis and optimization, reducing the manual tediousness of the post-silicon test effort; applications include pattern-set reduction, optimal test clock selection and adaptive test. Parametric-delay test can also be correlated to functional speed for speed-binning applications. Finally, parametric path delay tests can be used to validate statistical timing models. |
