| As integrated circuit (IC) technology advances to the sub-100nm region, power and associated thermal effects are becoming a limiting factor in high-performance circuit design. In addition to battery lifetime for mobile devices, power and temperature are emerging as concerns due to the strong temperature-dependence of leakage power, circuit performance, IC package cost and reliability. In traditional design methodologies, a constant worst-case power and temperature are commonly assumed, leading to excessive design margins (resulting in higher cost) or degraded performance due to temperature or power constraints. In reality, circuits exhibit strong workload-dependent variations (e.g. execution time, temperature) at runtime. Therefore, dynamically adapting a circuit to the behaviors of its workloads (trading off between performance, power, temperature and reliability) would enable reclamation of design margins from previous worst-case assumptions.; In this dissertation, improved runtime techniques are presented to attenuate power and thermal constraints on circuits by exploiting dynamic workload variations. These techniques include efficient dynamic voltage/frequency scaling (DVS) techniques, such as using feedback control and statistical information, to reduce circuit power consumption while maintaining performance requirements. This dissertation also explores the effect of temperature variations on circuit reliability, develops a reliability model subject to dynamic thermal stress, and investigates architectural techniques to maximize circuit performance without violating IC lifetime specifications. It is shown that, using these power- and temperature-aware runtime management techniques, substantial power and performance margins can be reclaimed from methodologies using worst-case power and temperature assumptions. In addition, the dynamic models developed in this dissertation can also be used for design time optimization. |
