| With the advent of deep sub-micron era (DSM), "System-on-chip (SOC)" has become a mainstream of IC industry. Semiconductor devices based on a smaller feature size offer the promise of faster and more highly integrated designs, but also provide a number of new challenges.; In SOCs, a large amount of communication time is spent on global multi-clock-period interconnects, which present themselves as the main performance limiting factor. How to handle global interconnects for performance optimization becomes an urgent issue. Another challenge is the increasing coupling effect (also known as crosstalk) between neighboring interconnects. Besides introducing noises on quiet interconnects, crosstalk could potentially change the interconnect delays and cause timing violations in the circuit. In this dissertation, we investigate and propose solutions to a few problems involving global interconnects and crosstalk.; To handle global interconnects, we propose techniques at different stages of the design flow. At physical layout stage, we propose to pipeline global interconnects by relocating flip-flops (an operation also known as retiming). Three efficient algorithms are designed to find an optimal retiming with the minimal clock period. We then solve the problem of retiming under both setup and hold constraints more efficiently than the best-known algorithm in the literature. We also consider clock skew scheduling for prescribed skew domains and give an optimal polynomial-time algorithm to minimize the clock period with possible delay padding. At clustering stage, we propose an iterative algorithm that finds an optimal clustering with the minimal maximum-cycle-ratio. At register transfer level (RTL), we use delay relaxation to do interconnect planning.; For crosstalk, we propose a circular time representation under which coupling detection is easier and more efficient than state-of-the-art approaches. Using the circular time representation, clock schedule verification with crosstalk is more efficient. We show that the trade-off between a level-sensitive latch and an edge-triggered flop can be leveraged in a sequential circuit design with crosstalk, so that the clock period is minimized by selecting a configuration of mixed latches and flops. We design an effective and efficient algorithm to solve this problem. |
