Design considerations for 400 GHz indium phosphide/indium gallium arsenide heterojunction bipolar transistors

The relatively wide bandgap, high low-field mobility, and high peak velocity of many compound semiconductors are inherent material advantages treasured by device engineers. For these reasons, InP and InGaAs compounds have emerged as the dominant semiconductor material system for Heterojunction Bipolar Transistors (HBTs) whose fT and fMAX exceeds 400GHz. High performance has been achieved through a combination of bandgap engineering and geometry scaling to delay the onset of Kirk effect and to reduce parasitic elements, respectively. This dissertation investigates the performance limitations of existing InP/InGaAs HBTs fabricated using a traditional mesa process and presents two methods to enhance performance.; Increases in the collector current density without sufficiently aggressive emitter area and voltage scaling have resulted in a rapid increase in the thermal resistance (RTH) and junction temperature (Tj) of state-of-the-art InP/InGaAs HBTs. Measurements in this dissertation show a fT increase of 8-10% with a 75°C decrease in Tamb. Estimations of Tj using measured RTH values show >75°C rise over Tamb due to self-heating at peak fT, indicating that 10% or more improvement in fT is possible if self-heating were minimized or eliminated. A 3-D thermal model has been developed to explore the thermal optimization of HBT design and predict RTH in an IC environment. A new experimental method to thermally de-embed the effects of the test environment has also been developed.; Velocity overshoot and quasi-ballistic transport, phenomena that occur readily in III-V materials, are expected to play a dominant role in device performance. Experimental data indicate that the electron velocity exceeds the steady-state velocity by a factor of two or more.{09}A 2-D electro-thermal model was developed to explore the nature of carrier transport through these devices. Several critical modifications to the device simulator and proper calibration of material parameters are discussed.; Finally, an adaptation of the Selective Implanted Collector, used in silicon bipolar transistors, is presented for InP/InGaAs HBTs. The new HBT structure, designated Selectively Implanted Buried Sub-collector (SIBS), is used to simultaneously reduce the collector transit time and base-collector capacitance. The electrical properties and scalability of SIBS is studied through a series of DC, CV, and RF measurements.