Efficient VLSI divide and conquer array architectures for multiplication

In this dissertation, we introduce an efficient VLSI array architecture for binary multiplication, and discuss its extension for vector-scalar multiplication. The architectures are based on an existing parameterized divide and conquer algorithm that uses optimal partitioning and redundancy removal for simultaneous computation of partial sums.; Four versions of the proposed Parameterized Binary Multiplier Architecture (PBMA), two for the general case where the multiplicand and the multiplier are variables (PBMA-A and PBMA-AT) and two for the special case where the multiplier is programmable constant (cPBMA-A and cPBMA-AT), are implemented and compared to the conventional Carry-Save Array Multiplier implementation. PBMA-A is optimized for area (A) and is shown to achieve significant area (A) savings at the cost of increased operational delay (T), while PBMA-AT is optimized for area-time product (AT) and is shown to achieve significant area-time product (AT) savings and a smaller operational delay (T) at the cost of smaller area (A) savings. cPBMA-A is optimized for area (A) and is shown to achieve significant area (A) savings without any major impact on operational delay (T), while cPBMA-AT is optimized for area-time product (AT) and is shown to achieve significant area-time product (AT) savings and a significantly smaller operational delay (T) at the cost of slightly smaller area (A) savings. All versions are also shown to be highly power (P) efficient.; Four versions of the proposed Parameterized Vector-Scalar Multiplier Architecture (PVSMA), two for the general case where the vector and the scalar are variables (PVSMA-A and PVSMA-AT) and two for the special case where the scalar is programmable constant (cPVSMA-A and cPVSMA-AT), are implemented and compared to the conventional parallel implementation with Carry-Save Array Multipliers. PVSMA-A is optimized for area (A) and is shown to achieve significant area (A) savings at the cost of increased operational delay (T), while PVSMA-AT is optimized for area-time product (AT) and is shown to achieve significant area-time product (AT) savings and a smaller operational delay (T) at the cost of smaller area (A) savings. cPVSMA-A is optimized for area (A) and is shown to achieve significant area (A) savings without any major impact on operational delay (T), while cPVSMA-AT is optimized for area-time product (AT) and is shown to achieve significant area-time product (AT) savings and a significantly smaller operational delay (T) at the cost of slightly smaller area (A) savings. All versions are also shown to be highly power (P) efficient.