| As the scaling of bulk Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFET) approaches sub-nanometer regime, different multiple-gate devices, specially, Fin Field-Effect Transistors (FinFET), are investigated as a superior alternative for classical planar MOSFETs. Implementation of these advanced non-classical devices is challenged by numerous new and difficult issues such as the formation of ultra-thin body and the control of its thickness and variability, appropriate tuning of metal gate work-function, fluctuations and statistical process variations, and, finally, the quantum nature of carrier transport in these nano-scaled devices. Therefore, simulation tools to design nano-scale transistors in the future require complex theory and sophisticated modeling techniques that can capture the physics of quantum transport accurately and efficiently. In this work an efficient algorithm termed Contact Block Reduction (CBR) method, based on nonequilibrium Green's function formalism, has been successfully utilized for the theoretical investigation of quantum transport in ultra-small FinFET devices. The simulator that utilizes the CBR method exhibits two key features needed for successful modeling and design. First, it is accurate, and second, it is fast, which allows one to investigate a large matrix of devices to obtain optimal device design.; This research is separated into two phases: (I) extensive modification, optimization and inclusion of new features into the existing two-dimensional (2-D) CBR simulator followed by the development of a new three-dimensional (3-D) self-consistent CBR transport simulator, and (II) rigorous analysis/optimization of nano-scaled FinFET device structures. In phase (II), the simulator was also utilized to explain available experimental data for a 10 nm n-type FinFET. Then, the geometry of the experimental device was optimized through numerous simulations to reach optimal characteristics as projected by the International Technology Roadmaps for Semiconductors (ITRS) for 22 nm high performance logic technology devices. The newly developed 3-D simulator was used for detailed analysis of device characteristics in extremely-scaled nano-FinFETs and the simulation results were compared with the corresponding 2-D simulations. Different features that could not be simulated using a 2-D simulator such as the effects of fin height and top gate on carrier transport, an influence of an unintentional dopant, were simulated using the 3-D simulator. |
