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Nanoscale stresses simulation and characterization of deep sub-micron semiconductor devices

Posted on:2007-03-16Degree:Ph.DType:Dissertation
University:University of VirginiaCandidate:Li, JianFull Text:PDF
GTID:1448390005463750Subject:Engineering
Abstract/Summary:
Stress is an increasingly important issue in semiconductor devices with the continuous reduction in device dimension. It can both degrade device characteristics by causing generation of electrically active defects, and it can enhance device performance by modifying local band structure and carrier mobility. In this work, we present a technique that combines FIB micro-machining, quantitative EDC imaging and analysis, finite element modeling (FEM) and/or semiconductor process simulations, and high-efficiency global minimization technique to measure stresses inside single crystal silicon region with a spatial resolution on the order of 10 nm and sensitivity on the order of tens of MPa.; Precisely controlled experimental EDC images of strained-Si MOSFETs were obtained. Initial stress simulations of theses devices were then created in FEM using the intrinsic stresses of the component materials measured by wafer curvature technique. The output files of the FEM, together with carefully defined TEM experimental conditions, were then used to generate an EDC simulated image. The difference map between the experimental and simulated EDC images was then created, and calibrated in term of stress differences. Stresses of the key component materials (low temperature oxide, TiSi2 and Poly-Si) were then varied independently in the FEM model until a best match is found between these two images. Once this is done, the effects of the surrounding materials on the stress distribution in the strained-Si channel devices are studied quantitatively. The results show that the stress distribution in the strained-Si channel is very sensitive to the stress state of the surrounding materials, especially TiSi2, which can modify the stress distribution in the channel by well over 100 MPa. The accuracy of our stress quantification method is now established at the few tens of MPa level.; In collaboration with Micron Technology, this technique has been applied to measure stress fields in high density DRAM cells. Our results show that optimized shallow trench isolation fills lead to improved leakage current and retention time characteristics. In collaboration with IBM, the EDC technique has been applied in conjunction with the process simulation program TSUPREM 4. Stress measurements were also correlated between EDC and CBED (Convergent beam electron diffraction) techniques, showing a good match.
Keywords/Search Tags:Stress, EDC, Devices, Semiconductor, Technique, FEM
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