| The first part of this dissertation presents an all-digital modulator to be used in a software-defined radio (SDR) transmitter. A digital-controlled oscillator (DCO) followed by two digital phase rotators (DPR) are the main building blocks. The DCO and DPRs are enclosed, respectively, by a phase-locked loop and two delay-locked loop. These Loops are fully digital and their functions, including filtering and calibration are all performed in a digital signal processor (DSP). The chip was fabricated in a 90nm CMOS process by ST semiconductor and tested for GSM and WCDMA. The total area of the chip is 3 mm2 and current consumption is 30 mA for the semi-analog blocks (DCO core, DPR core and their buffers), 25 mA for the digital processor, and 70 mA for the phase-to-digital converter. The last one can be reduced by 30 percent by gating off the circuit during idle times.;The second part is devoted to mostly theoretical subjects. A simple but accurate method is introduced to simulate the frequency pulling effect in oscillators. The jitter performance of multiplying delay-locked-loops (MDLL) is studied and compared with that of the ring oscillators. Theoretical calculations are validated with experiments and behavioral simulations. A simple model is introduced that can be used to simulate the effect of various noise sources in a complete MDLL system. Also, a study of quadrature oscillators has been done and presented in this part. Geometrical interpretations gives insight into better understanding the essential phenomena in quadrature oscillators, such as various modes of operation and their stability. The effects of different kinds of mismatches on the behavior of the oscillator are extensively investigated, and precise mathematical formulas are derived based on a geometrical interpretation. |
