VLSI architectures and implementations of iterative FEC decoders

Forward error correcting (FEC) codes are essential parts of digital communications systems. As the demand for content-rich applications and ubiquitous wireless services has grown, research interests have moved to advanced coding schemes such as turbo codes and low-density parity-check (LDPC) codes that use iterative decoding to achieve excellent performance. A decoder implementation for these advanced codes must be optimized at all aspects of its design phases in order to realize a competitive solution. In this dissertation, we present the various design techniques of three iterative decoders.;A low-complexity decoder chip that employs the efficient layered decoding message passing algorithm and the offset Min-Sum check algorithm for irregular QC-LDPC codes has been developed in TSMC 0.18-mum CMOS. With sequential processing units, consolidated memory architectures and optimized computation scheduling, this programmable chip can decode all QC-LDPC codes in the Mobile WiMAX standard for significantly reduced complexity. It achieves 68-Mbps decoding throughput with 55K logic gates. Its measured power consumption is 149.8-mW at 1.8V, and the corresponding energy consumption is 220 pico-Joule per bit per iteration.;A QC-LDPC decoder based on the delta-based layered decoding message passing algorithm has also been developed in 0.18-mum CMOS for high-throughput applications. The algorithm suffers a slight performance degradation from the ideal layered-decoding message-passing algorithm. We have developed a simple matrix permutation procedure to obtain an optimized computation scheduling to mitigate the performance degradation. The decoder achieves 287-Mbps decoding throughput with an estimated power consumption of 836 mW from 1.8V for the WiMAX codes. Its energy consumption is 291 pico-Joule per bit per iteration.;A 150-Mbps turbo FEC code was proposed in the HomePlug AV standard for high-speed home-networking systems over in-house power lines. We demonstrate an efficient architecture for the FEC core to meet the high throughput requirement with lowered latency and memory overhead. This is realized by combining radix-16 encoding with a time-shared conflict-avoidance memory-access structure in the encoder, and by employing an optimized sub-bank parallel decoding architecture for the iterative decoder.