Digital calibration methods for sample-and-hold circuits

An important analog building block for a broad range of analog-to-digital converter (ADC) architectures is the sample-and-hold (S/H) circuit. Unfortunately, the S/H suffers from a number of nonidealities. Two such nonidealities are bandwidth mismatch between S/H circuits in time-interleaved analog-to-digital data converters (TIADCs) and the input signal dependent on-resistance of the S/H switch. Both nonidealities create distortion in the output spectrum which limits the signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of the ADC. Thus methods which can improve the SNDR/SFDR are desirable. This manuscript develops models of the bandwidth mismatch and the input signal dependent on-resistance of the S/H switch. These models are utilized in the development of digital domain calibration algorithms capable of removing the distortion. Numerical simulations demonstrate that the proposed digital calibrations increase SFDR at a relatively modest computational cost.