Cryogenic operation of silicon-germanium heterojunction bipolar transistors and its relation to scaling and optimization

The objective of the proposed work is to study the behavior of SiGe HBTs at cryogenic temperatures and its relation to device scaling and optimization. Not only is cryogenic operation of these devices required by space missions, but characterizing their cryogenic behavior also helps to investigate the performance limits of SiGe HBTs and provides essential information for further device scaling. Technology computer aided design (TCAD) and sophisticated on-wafer DC and RF measurements are essential in this research.;Drift-diffusion (DD) theory is used to investigate a novel negative differential resistance (NDR) effect and a collector current kink effect in first-generation SiGe HBTs at deep cryogenic temperatures. A theory of positive feedback due to the enhanced heterojunction barrier effect at deep cryogenic temperatures is proposed to explain such effects. Intricate design of the germanium and base doping profiles can greatly suppress both carrier freezeout and the heterojunction barrier effect, leading to a significant improvement in the DC and RF performance for NASA lunar missions.;Furthermore, cooling is used as a tuning knob to better understand the performance limits of SiGe HBTs. The consequences of cooling SiGe HBTs are in many ways similar to those of combined vertical and lateral device scaling. A case study of low-temperature DC and RF performance of prototype fourth-generation SiGe HBTs is presented. This study summarizes the performance of all three prototypes of these fourth-generation SiGe HBTs within the temperature range of 4.5 to 300 K. Temperature dependence of a fourth-generation SiGe CML gate delay is also examined, leading to record performance of Si-based IC. This work helps to analyze the key optimization issues associated with device scaling to terahertz speeds at room temperature. As an alternative method, an fT-doubler technique is presented as an attempt to reach half-terahertz speeds. In addition, a roadmap for terahertz device scaling is given, and the potential relevant physics associated with future device scaling are examined. Subsequently, a novel superjunction collector design is proposed for higher breakdown voltages. Hydrodynamic models are used for the TCAD studies that complete this part of the work. Finally, Monte Carlo simulations are explored in the analysis of aggressively-scaled SiGe HBTs.;A significant amount of this work has been published or submitted for publication at various refereed conferences and journals, including IEEE International Electron Device Meeting [18], IEEE Transactions on Electron Devices [19]-[22], IEEE Bipolar/ BiCMOS Circuits and Technology Meeting [23]-[27], IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems [28], and IEEE Microwave Theory and Wireless Component Letters [29]. Master level research prior to this work was completed in 2007 [30]. More specifically, details of this dissertation can be found in the following refereed publications: (1) Discovery, explanation, and simulation of a novel cryogenic negative differential resistance effect and a collector-current kink effect in first-generation SiGe HBTs (Chapter II, also published as [18]). (2) Modeling of the above novel effects and study of their circuit implications (Chapter II, also published as [19]). (3) Base profile optimization for improved RF performance at 43 K (Chapter III, also published as [25]). (4) Record fmax achieved for all silicon-based technologies (Chapter IV, also published as [23]). (5) The fastest CML/ECL gate delay achieved for all silicon-based technologies and the first report of the temperature dependence of intrinsic base sheet resistance in third-generation SiGe HBTs (Chapter IV, also published as [22]). (6) A scaling path for SiGe HBTs explored through its relation to cryogenic operation of prototype fourth-generation SiGe HBTs (Chapter V, also published as [21]). (7) First demonstration of the fT-doubler technique in third-generation SiGe HBTs to achieve half-THz performance (Chapter V, also published as [28]). (8) Invention of a superjunction collector design in high-speed bipolar transistors to improve the speed/breakdown tradeoff (Chapter V, also published as [27]).