A reliable design flow for platform FPGAs

Aggressive technology scaling over the years has led to increased levels of integration and heterogeneity in the design fabric of Field Programmable Gate Arrays (FPGAs). Platform FPGAs today have evolved from mere prototyping devices to powerful domain-specific reconfigurable processors. Traditionally FPGA design flows have been designed to optimize the resulting design for area, performance, and power consumption. Such deterministic optimization techniques are oblivious to the changes in the device characteristics due to variations during the manufacturing process and their subsequent degradation in time due to various operational stress phenomenon. Additionally, as the device feature sizes shrink the impact of operation conditions such as temperature and supply voltage on the lifetime degradation of components increases exponentially. Consequently, the resulting designs are sub-optimal in performance and result in a low mean time to failure MTTF of the target FPGA platform. In this work we address the impact of various aging based failure mechanisms, and process variations on the reliability, performance, and power consumption of the resulting design. We present a tool flow that models the device degradation characteristics and incorporates heuristics based on such an analysis into various key stages of the FPGA design flow. We also studied the impact of process variations on various routing elements of an FPGA and developed a statistically intelligent routing algorithm SIRA to improve the timing and power yields of the target design. We then studied the temperature variations both across and with-in designs by developing a thermal estimation tool Tprof. The thermal map generated by Tprof was used to analyze the impact of temperature variations on the lifetime reliability of platform FPGAs. We then explored the impact of voltage variations in dual-Vdd based FPGA architectures on lifetime reliability and power consumption of platform FPGAs. The insights acquired by analyzing the device degradation and lifetime characteristics were used to incorporate reliability and degradation awareness into various stages of the design flow. We plan to extend the reliability frame work to study the impact of process variations on thermal and voltage dependent intrinsic failure mechanisms. We also plan to validate the reliability framework by integrating it into FANTOM, an Algorithm Architecture Co-design framework.