| The increased level of integration in current system-on-chip (SoC) solutions for wireless transceivers, targeted at size and cost reduction, creates an increased potential for self-interference, which is suffered in one part of the system as a result of activity in another.;The aggressing functions, where the interference originates, may be digital circuits, RF circuits, or analog functions. Likewise, the victim function, where the interference is suffered, may be of either type, but is typically a sensitive analog function.;This work presents principles and design approaches associated with interference mechanisms that are encountered in the SoC environment, and proposes a novel phase-avoidance approach for mitigating the impact of specific self-interference mechanisms, thus complementing the commonly used frequency and time avoidance approaches.;The proposed technique is demonstrated in detail for one particular problem, referred to as the 'integer-N channel' interference problem, wherein the transmitter is tuned to an integer multiple of the frequency source that serves as the reference input to the phase-locked loop (PLL) that is used to generate the phase-modulated carrier. In this interference mechanism, the harmonic relationship between the aggressing high-frequency signals and the low-frequency reference source (a 26MHz clock in this case) results in excessive jitter that is experienced in this reference clock signal and consequently in incompliant phase-trajectory-error (PTE) performance for the modulated signal produced by the PLL.;The demonstrated solution to the integer-N channel interference problem, whose development was a major part of this work, is implemented in a 90nm CMOS GSM transceiver SoC, where it relies entirely on software algorithms that do not necessitate any hardware changes in the existing design. Such approach offers time-to-market and cost advantages, as a hardware redesign and fabrication cycle is costly and time-consuming.;Two additional interference problems are presented in detail, including measured data and analyses, for which the proposed phase-adjustment approach is shown to be applicable.;A great part of this work is dedicated to the development of measurement procedures and mathematical analyses that were necessary for the identification of the components in the presented interference mechanisms. Additionally, this work categorizes interference problems that may be addressed by the proposed phase-domain approach, and defines the general conditions for the applicability of the proposed phase-adjustment technique.;More generally, a design-for-interference-mitigation (DfIM) approach is advocated in which specific provisions are to be made in integrated solutions to allow for software solutions to be implemented once interference problems are encountered in a fabricated device. |
