Power modeling and management for adaptive multi-core processors

This dissertation investigates the problem of modeling and managing power for adaptive chip multi-core processors (CMP). Parameter variation due to manufacturing error will be an unavoidable consequence of technology scaling in future generations. The impact of random variation in physical factors such as gate length and interconnect spacing will have a profound impact on not only performance of chips, but also their power behavior. People requires a better understanding and modeling on the variation at a higher level without facing the daunting task to learn the underlying physical details. And the management of the power on a global chip-wide and local single function structure becomes significantly complicated if considering the sharing of the power and resources among multiple competing sources. Though many optimizations have been proposed and many of them effectively improve the power/performance efficiency. Understanding these methods, and accordingly adapting, combining existing mechanisms, and inventing new techniques to better manage the power in CMPs is critical.;In this work, we develop architecture level models that model power variability due to manufacturing error and examine its influence on multi-core designs. We introduce Vari-Power, a tool for modeling power variability based on a micro-architectural description and floor-plan of a chip. In particular, our models are based on layout level SPICE simulations and project power variability for different micro-architectural blocks using statistical analysis. Using VariPower, we characterize power variability for multi-core processors, design a variation-aware cache structure and explore the application sensitivity to power variability.;Also in this work, we introduce an adaptive, multi-optimization power saving strategy for multi-core power management. Specifically, we solve the problem of meeting a global chip-wide power budget through run-time adaptation of highly configurable processor cores. Our approach applies analytic modeling to reduce exploration time and decrease the reliance on trial-and-error methods. We also introduce risk evaluation to balance the benefit of various power saving optimizations versus the potential performance loss. Overall, we find that our approach can significantly reduce processor power consumption compared to alternative optimization strategies.;Finally, we study a few resource management mechanisms used for shared caches in CMPs. We showed the pros and cons of the methods by providing detailed and objective comparison among them. We proposed a new technique that provides both a coarse and fine-granularity management for the shared-cache and the results prove our method provide the best power/performance efficiency.