All-digital Clock and Data Recovery architectures

Clock and Data Recovery (CDR) circuits form an indispensable part of a Serializer-Deserializer system. Once the equalizer removes the distortion, the CDR circuit can recover the incoming data. There are two main types of CDR circuits---digital and analog. This classification is based on the phase detection mechanism employed. Several challenges emerge in this regard. A linear phase detector mechanism is not realizable at high speeds due to technological constraints. A digital phase detector results in a system that is dependent on the jitter distribution of the input signal. A compromise between the two extremes is to employ oversampling in the phase detector.;A novel Multiple-Rotating-Clock-Phase (MRCP) oversampling all-digital data recovery architecture has been proposed and implemented on a field-programmable device. This architecture uses a multi-phase oscillator. A stable and robust data detection window is derived from the oscillator phases that also rotate to track the data.;It is not efficient or possible to simulate a CDR system at gigabit per second data rates in a transient fashion. In this work, novel simulation techniques have been presented to reduce the transient simulation time for jitter tolerance characterization. The main idea is that the maximum slope of the jitter sinusoid is the reason for transient bit errors and the entire sinusoid need not be used.;Exact equations have been derived in this dissertation for an oversampling phase detector with a general oversampling ratio and inter-phase spacing in the presence of random, deterministic and asymmetric jitter. An interactive MathematicaRTM program using symbolic analysis is developed for this purpose. These equations can be used in a behavioral simulator to perform system-level analysis at an early design stage using phase domain simulation methods.