Thermal management methodology for FPGAS

Field Programmable Gate Arrays (FPGAs) are emerging from their traditional role as prototyping devices and are gaining popularity in commercial applications ranging from embedded control systems to power critical mobile devices. Aggressive efforts are being made to improve performance and reduce power dissipation and area to compete with custom ICs. In conjunction with technology scaling, this has resulted in high power densities and rigorous performance requirements. Previously considered second order effects have now stepped into the forefront, the most important being temperature and leakage power dissipation. The consequences of excessive temperatures and non uniform thermal gradients include circuit failure, performance degradation due to slower transistor switching speeds and interconnect delays and leakage runaway due to the exponential cyclic relationship between temperature and leakage power. In light of the detrimental effects of temperature on future FPGA systems, it is essential to accurately profile and minimize temperatures and temperature gradients at early stages of the design flow.;In this dissertation, our focus is on the system level management of temperature distribution across FPGAs. We developed a comprehensive framework comprising of innovative algorithms and architectures to create a robust approach to manage on-chip temperatures. Temperature management solutions require a light weight but accurate model of a device's thermal activity. The model should be portable and computationally convenient. In that regard, we adapted the resistive mesh model for thermal profiling of FPGAs. The model exploits the characteristic structural elements of the reconfigurable fabric to produce an efficient and accurate thermal estimate. Accurate power estimates are essential to thermal profiling. Unlike in custom ICs, uniformly arranged switch boxes, connection boxes and fixed routing channels make interconnect power estimation in FPGAs distinct. We developed an accurate and efficient model to estimate total FPGA interconnect capacitance, dynamic and leakage power prior to routing. Our methods derive the estimates based on predicted values of routing congestion and interconnect resource utilization. We then extended the model to accommodate complex segmented routing architectures and formulated relations to generate post place capacitance and power estimates of individual routing channels. The interconnect power distribution estimates were combined with logic power to generate thermal maps of the reconfigurable fabric using our thermal model. We employed the thermal maps within a temperature driven placement tool targeted specifically for FPGAs. Our placement tool achieved a significant temperature reduction and produced a more uniform thermal distribution with minimal impact on wirelength. Recognizing the need for methods that intelligently modify their response during run time based on current thermal conditions we developed a novel and robust simulation framework exploring adaptive techniques to reduce FPGA temperatures. We implemented a thermal driven voltage scaling algorithm based on temperature and performance feedback. Our performance estimation model is an accurate empirical relation between delay, supply voltage and temperature with a small average error.