Power, variation and reliability optimization for FPGAs in nanometer technologies

As CMOS technology continue to scale down to nanometer, increased power consumption, worsened process variation and degraded device reliability become crucial constraints for VLSI systems including field programmable gate arrays (FPGAs). This dissertation proposes novel circuits, architectures and CAD algorithms for FPGA power, variation and reliability optimization.;To reduce FPGA power consumption, we design novel Vdd-programmable and Vdd-gateable interconnect switches with minimal number of configuration SRAM cells. We then evaluate Vdd-programmable FPGA architectures using the new switches. The best architecture in our study uses Vdd-programmable logic blocks and Vdd-gateable interconnects.;To reduce the leakage power of Vdd-level converters, we first propose two ways to avoid using level converters in interconnects. The first method enforces that there is only one Vdd-level within each routing tree while the second method can have different Vdd-levels within a routing tree, but no low-Vdd switch drives high-Vdd switches. We then develop various dual-Vdd assignment algorithms considering chip-level time slack allocation for maximum power reduction. Considering process variation and pre-routing interconnect delay uncertainty, we present the first in-depth study on stochastic physical synthesis algorithms leveraging statistical static timing analysis (SSTA). We also study the interaction between each individual design stage by applying various stochastic algorithms concurrently.;Concerning the degraded timing yield of the deterministic Vdd-level assignment algorithm with process variation, we present two statistical Vdd assignment algorithms. The first greedy algorithm is based on sensitivity while the second one is based on timing slack budgeting. Both minimize chip-level interconnect power without degrading timing yield.;Considering the degraded device reliability with the continuous technology scaling, we first show that FPGA chip-level transient soft error rate (SER) can no longer be ignored. We then develop an efficient, yet accurate, chip-level transient SER evaluation method. We finally perform device and architecture concurrent optimization considering hundreds of device and architecture combinations.;To the best of our knowledge, this dissertation provides the first in-depth study on novel CAD algorithms for Vdd-programmable FPGAs, stochastic physical synthesis for conventional and also Vdd-programmable FPGAs, and FPGA transient SER optimization.