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System and IC level analysis of electrostatic discharge (ESD) and electrical fast transient (EFT) immunity and associated coupling mechanisms

Posted on:2009-04-04Degree:Ph.DType:Dissertation
University:Missouri University of Science and TechnologyCandidate:Koo, Ja YongFull Text:PDF
GTID:1442390002492146Subject:Engineering
Abstract/Summary:
The exposure of electronic circuits to lightning, electrostatic discharge (ESD), electrical fast transients (EFT) or sine wave signals can reveal RF immunity problems. Typical problems include temporary malfunctions or permanent damage of integrated circuits (ICs). In an effort to reproduce those disturbances, a series of electromagnetic compatibility standards has been developed. However, a complete understanding of the root cause of the immunity problems has yet to be established. This dissertation discusses immunity problems in three papers, starting at the system level, via the coupling path into the IC. The first paper analyzes system level ESD testing, wherein a Round Robin test was conducted at three different locations to investigate ESD test repeatability. It allowed a correlation of parameters that describe the severity of an ESD generator with respect to failure levels observed in equipments under test (EUTs). The results demonstrate the importance of the transient field generated by ESD generators for obtaining test result repeatability and indicate narrowband coupling between the ESD generator and the EUT. The second paper presents and analysis of the coupling path. This method analyzes the coupling path under the assumption of linearity in the frequency domain. Further, it shows the limitations of the small signal assumption caused by the non-linear effects of active devices. The third paper analyzes the immunity of ICs against the noise generated from EFTs with emphasis on the power delivery network (PDN). A methodology for obtaining and analyzing a circuit model of PDN inside an IC is provided. The model includes the ESD protection diodes as well as passive elements between power and ground pins. This allows estimating the current sharing of different branches within the IC and an analysis of the reaction of ESD power rail clamp to overvoltage conditions.
Keywords/Search Tags:ESD, Immunity, Coupling, System, Level
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