Algorithm Design And Implementation Of FFT Demodulators And Channel Decoders For OFDM Systems

Orthogonal frequency division multiplexing(OFDM)is the fundamental solution for multi-carrier transmission.In the leading broadband wireless communication standards as LTE-Advanced and IEEE 802.11ac/ad/ay,OFDM is the enabling technology for high-data-rate transmission.Meanwhile,with the advent of Internet of Things(IoT),OFDM is also selected by 3GPP as one of the candidate solutions for realizing the machine-type communications(MTC).Fast Fourier transform(FFT)and channel decoding are consid-ered as the key issues for OFDM,since FFT is responsible for OFDM signal demodulation,and channel decoding is an indispensable part of a robust system.Therefore,designing efficient FFT modules and channel decoders from both algorithmic level and architec-ture level for OFDM system is of great value and has drawn continuing attention from academia and industry,which also serves as the motivation of this dissertation.The main work and contributions of the dissertation are in the following aspects:Firstly,the transmission bandwidth of OFDM signal has been expanded to hundred-s or thousands of megahertz(MHz),which drives the FFT module to be upgraded to have the parallel processing capability.Therefore,designing a parallel FFT computing module with low hardware expense becomes a key issue for OFDM system.In existing literatures,multi-path delay feedback(MDF)and multi-path delay commutator(MDC)are extensively-used hardware schemes for parallel FFT processor,while neither of the solutions can achieve full utilization of both arithmetic resources and memories.In this dissertation,a new parallel FFT computing scheme is derived from the discrete Fouri-er transform(DFT)matrix.By further utilizing the folding transformation to rearrange the arithmetic operations at the underlying level,the mixed-decimation multi-path delay feedback architecture is designed for realizing parallel FFT.Without degrading the per-formance of throughput and latency,the proposed design occupies the same amount of memories as the MDF structure and meanwhile,it consumes the similar number of com-plex adders and rotators as the MDC structure,which allows a lower overall hardware cost than the existing design.Secondly,the signal-to-quantization-noise ratio(SQNR)of computing results serves as a kernel figure of merit in realizing FFT.It can be recognized that the FFT implementa-tion has primarily followed the hardware-friendly radix-2~kalgorithm,which motivates the fixed-point analysis of radix-2~kalgorithm in the dissertation.To gain a general result,the radix-2~kalgorithm is first expanded as the mixed-order radix-2~kalgorithm by loosening the constraint on the radix order k,and the involved arithmetic operations are matricially expressed.Then the quantization effects of the mixed-order radix-2~kalgorithm is ana-lyzed with reconfigurable wordlengths.Based on the obtained error propagation model,a closed-form expression to estimate the SQNR of FFT output is derived.Experimen-tal verifications suggest the estimated SQNR can coincide with actual values.Note that the setting of the radix order and wordlengths for a FFT processor will impact both the computing accuracy and the hardware cost,it is visible to achieve a reasonable tradeoff between the two metrics through parameter optimization.To this end,the hardware re-quirement of the mixed-order radix-2~kalgorithm using different pipelined architectures is evaluated,and then a heuristic search using Simulated Annealing is proposed to joint op-timize the radix order and wordlengths.Compared to the existing work that only involves the wordlength optimization,the further consideration of the radix order in the proposed strategy can better utilize hardware resources to improve FFT computing accuracy.In terms of channel coding,the dissertation first investigates turbo codes that are widely used in the OFDM broadband wireless transmission system.The quadratic per-mutation polynomials(QPP)interleaver is a representative pseudo-random interleaver for turbo coding,it is applied to control the access of parallel soft-input-soft-output(SISO)de-coding modules to extrinsic information.Under the high decoding parallelism,the ran-domness of interleaving addresses render the conflict-free access of extrinsic information a challenging work and meanwhile,the implementation of parallel QPP interleaver will suffer from high hardware complexity.These problems will hinder the realization of high-throughput turbo decoder.To tackle these problems,the data interaction between SISO decoding modules and memory instances for caching extrinsic information is in-vestigated under different strategies.On this basis,a storage pattern that enables the ex-trinsic information to be concurrently accessed without collisions is proposed,which is available for different decoding strategies and parallelism.On the other hand,the alge-braic properties of QPP function are exploited to simplify computations related to address generation and data access,and thus a low-complexity hardware structure for parallel QP-P interleaver is designed.Compared with the existing work,the proposed design is less hardware consuming and reveals usability for different decoding strategies.The convolutional codes are selected by MTC equipment to assist the delivery of con-trol information and short messages in IoT.MTC devices are usually deployed at remote locations with confined transmission power for extending battery life,and these factors result in a higher demand for receiver sensitivity to ensure reliable transmission.Accord-ingly,list decoding becomes more practical than the Viterbi decoding for convolutional codes as the former has a enhanced error-correction capability.The published literatures reveal low efficiency for hardware implementation,since the list decoding schemes for non-tailbiting codes will consume enormous memories,and the counterparts for tailbiting codes suffer from formidable computational complexity.To circumvent the foregoing ob-stacles,the internal relations among the multiple decoding sequences of the non-tailbiting codes are demonstrated and described using path identifers,then a parallel list decoding algorithm assisted by the path identifer is proposed,which can eliminate the redundant data storage of backtracking and thus avoid the excessive use of memories.For tailbiting codes,the circularity of the trellis is utilized to derive a reliability-ordered initial state esti-mator,which can narrow the trellis searching space without incurring errors to the finding of decoding sequences.With the deployment of the proposed initial state estimator,the tailbiting list decoder is able to occupy fewer arithmetic resources than existing solutions while preserving the optimal error-correction performance.