Research And Design Of Low Latency And High Reliable Display Chip For Edge Computing

With the development of 5G network technology,the number of devices connected to the network and the amount of data generated in the edge devices are increasing rapidly,which brings a lot of burden to the mobile network infrastructure.In this de-velopment trend,it is difficult for cloud computing service model to maintain the real-time responding performance to edge devices.A new model called edge computing can reduce the amount of terminal data transmission by migrating part of the processing burden to the terminal devices or network links.In edge computing,the performance of human-computer interaction system is particularly important for user experience,and display devices are the most important bridge of human-computer interaction.There-fore,the low latency and high reliable display systems are of great value to edge com-puting.This dissertation focuses on the research of three key technologies of human-computer interactive display system in edge computing devices,including real-time performance,low-power consumption and reliability.Through the design optimization in algorithm,architecture,system and chip levels,the display chip for low power,low latency and high reliable applications is realized.The main research work and innova-tions are as follows:(1)According to the real-time requirement,a heterogeneous graphics computing system architecture suitable for edge computing is proposed.The efficient graphics processing is realized by balancing the computing load in different stages of pipelines and designing the architecture of vertex and fragment heterogeneous accelerator.The chip test results show that the maximum frequency of single graphics processing core can reach 200MHz when only the other computing units are disabled.Through the typical edge computing scenario test,it shows that the highest pixel processing speed is 152 MPixels/s,and the performance per watt is 5.8 times higher than that of ARM microprocessor chip STM32L476 for low-cost display system.(2)Due to the limitation of power consumption and memory bandwidth,a block-based real-time frame buffer compression algorithm is proposed,and the compressor architecture is designed.Through the synchronous compression of the pixels when reading frame data,the bandwidth requirement of the computing unit can be reduced without affecting the system performance.On the Kintex-7 FPGA based test platform,the graphics processing system and frame buffer compressor are transplanted and tested by running a typical interface.Compared with the JPEG frame buffer compression method,the system power saving effect is 2.3 times higher.(3)According to the requirement of reliability,a fault-tolerant algorithm of sys-tolic array with multi-period accumulation redundancy information is proposed,and the architecture of fault-tolerant systolic array is designed.The fault injection experimental results show that the error recovery rate can reach 99%.The fault recovery rate is bet-ter than time-space redundancy,which is suitable for deep learning applications.The design is synthesized by Synopsys tools and compared with dual-mode redundancy ar-chitecture.Results show that the redundant area is 61.5%if using 32 bit multiplication units.Therefore,it saves 38.5%of the redundant area.Compared with the migration redundancy method,it can realize the detection of random errors and error recovery.(4)An energy-efficient display chip based on RISC-V extended instruction set is designed and fabricated.At room temperature,the power consumption of the chip system is 65 mW,which is 3 times lower than that of the research results of the unified shader graphics processing chip in academia,and 1.49 times higher than that of the mainstream ARM based microprocessor chip STM32L476.Through the algorithm,architecture,system levels of software and hardware col-laborative optimization design and low power design in chip level,the high-efficiency,high-reliability display chip for edge computing is realized.