The Fabrication And Research Of Ferroelectric Field Effect Transistors Based On Indium Oxide Nanowires And Molybdenum Disulfide

Transistor is the foundation of modern integrated circuits.With the increase of chip integration level,the scaling down of the metal-oxide-semiconductor field effect transistor?MOSFET?is becoming more and more difficult.On the one hand,the size of bulk material silicon has scaled down to its physical limit,so it is necessary to find new low-dimensional semiconductor materials to achieve further reduction in transistor channel size.In recent years,one-dimensional semiconductors represented by semiconductor nanowires and two-dimensional semiconductors represented by layered molybdenum disulfide have become research hotspots,and are expected to become substitutes for silicon in transistors.On the other hand,the dielectric constant of the gate dielectric layers in the transistor needs to be continuously increased to achieve a reduction in their equivalent thickness.Among different kinds of dielectrics,ferroelectric materials generally have a high relative dielectric constant.In addition,the residual polarization characteristics of the ferroelectric layer can be used in non-volatile semiconductor applications.In recent years,it has also been found that the negative capacitance effect of the ferroelectric dielectric layer can be used to amplify the modulation effect of the gate voltage,and achieving effective suppression of non-ideal subthreshold currents in the field effect transistor.Therefore,ferroelectric field effect transistors containing ferroelectric materials in the gate stack have great application potential in both logic devices and memory devices.Compared with MOSFETs,the biggest advantage of ferroelectric field effect transistors is their low power consumption,which is beneficial to the improvement of device integration.In order to combine the advantages of low-dimensional semiconductors and ferroelectric field effect transistors in improving device integration capabilities,in this paper,we have studied the performance,working mechanism and application of three different types of ferroelectric field effect transistors based on indium oxide nanowires and molybdenum disulfide.The specific work is as follows:1.High-performance ferroelectric memory based on side-gated In₂O₃ nanowire FETs.Recently,ferroelectric field-effect transistors?FeFETs?have received considerable amount of attention due to their low power consumption and high memory density in non-volatile memory applications.Here,we design and achieve a new type of FeFETs using the single In₂O₃ nanowire and poly?vinylidene fluoride-trifluoroethylene?copolymer with a unique side-gated architecture along with a simple fabrication process.There is not any other manufacturing process required after the deposition of the organic ferroelectric film,avoiding any post-deposition damage to the organic film as well.It is noted that our devices exhibit excellent performances including the large on/off ratio?>10⁶?,insignificant leakage current?<10^-1212 A?and stable retention characteristics at room temperature.In particular,the memory hysteresis characteristics can be effectively modulated by adjusting the side-gate geometries.All these results have indicated the great potency of ferroelectric side-gated In₂O₃ NW structures for high-performance non-volatile memory applications.2.Development of In₂O₃ nanowire negative capacitance field-effect transistor.The power consumption of conventional MOSFETs is fundamentally limited by the Boltzmann distribution,causing that the subthreshold swing?SS?of the device con not be less than 60 mV/dec at room temperature.Herein,we present a kind of high-performance In₂O₃ nanowire negative capacitance field-effect transistor?NC-FET?by introducing a ferroelectric P?VDF-TrFE?layer into the gate dielectric stack.The 1-D geometry advances and desirable dielectric constant of In₂O₃nanowires make it easy to meet the capacitance matching in NC-FETs.The fabricated devices exhibit excellent gate modulation properties with high saturation current density about 550?A/?m and outstanding SS value less than 60 mV/dec for over 4decades of drain current.The assembled inverter circuit based on In₂O₃ NC-FETs can demonstrate a voltage gain of 25 and a cut-off frequency of larger than 10 MHz.Moreover,short channel devices have been fabricated by utilizing a self-aligned fabrication scheme.When the device channel length is scaled down to 200 nm,the superior performance of single NW devices can be achieved with the high on/off current ratio of>10⁷,large output current density of 960?A/?m and small SS value of42 mV/dec.All these results demonstrate the potency of nanowire based NC-FETs for the facilitation to break through Boltzmann limit in nanoelectronics,and have expanded the applicable field of the NC-FETs.3.Optimization of top-gated MoS₂ transistors using ferroelectric dielectric structure.A certain hysteresis phenomenon usually occurs in the top-gated field effect transistor?FET?based on two-dimensional MoS₂,which affects the practicability of MoS₂.The non-destructive deposition process and good passivation effect of the organic dielectric PMMA can greatly reduce the trap density in the semiconductor/insulator interface.However,since the dielectric constant of PMMA is relatively low,devices with PMMA dielectric layer often require a large operating voltage.In order to solve this problem,we combined the low-k PMMA and the high-k P?VDF-TrFE?to form a gate stack,and successfully assembled MoS₂ top-gated transistors with P?VDF-TrFE?/PMMA bilayer dielectric.The device maintains good interface characteristics of the MoS₂/PMMA interface and exhibit hysteresis-free operation characteristics.At the same time,the transistor can be dully modulated under gate voltage within 4 V,and the on/off ratio is larger than 10⁶.The interface state density of the device is as low as 6.8×10¹¹ cm^-2/eV,which has been significantly reduced compared to the previous MoS₂ top-gated transistors.Moreover,we have characterized the low-frequency noise of the device and proved that the 1/f noise in the MoS₂ transistor with P?VDF-TrFE?/PMMA bilayer dielectric is caused by the carrier number fluctuation;this is consistent with the MoS₂ transistor using SiO₂ as the dielectric layer.This work provides a practical method for optimizing the gate stack of MoS₂ top-gated transistors,which can be used to achieve hysteresis-free and low voltage operation.