Physical Model Of SBT Gated Ferroelectric Field Effect Transistor Based On Negative Capacitance Effect

The ferroelectric field effect transistor(FET)is based on the traditional metal-oxide-semiconductor field-effect transistor(MOSFET)to replace the traditional gate oxide material with the ferroelectric material.In recent years,FRAM,which is composed of ferroelectric field effect transistors(FETs),has attracted much attention and has been recognized as one of the most promising memories in the next generation.Because this kind of memory has some excellent characteristics,including fast storage speed,non-volatile and anti-radiation performance,and so on.With the deepening of the information society,the chip integration level is increasing,power consumption has been a serious problem for people.It is shown that the negative capacitance effect of the ferroelectric can reduce the sub-threshold swing of field effect transistor and reduce the power consumption of the transistor effectively.Based on this,the negative capacitance effect of ferroelectric field effect transistors is studied by combining theoretical modeling with numerical analysis.The specific elements and conclusions are as follows:(1)Based on Landau-Ginzbug-Devonshire phenomenological model,Poisson equation and current continuity equation,the negative capacitance SBT ferroelectric gate field effect transistor is established and the influence of temperature on its electrical performance is analyzed.The results show that the temperature has a certain effect on the electrical properties of negative capacitance SBT field effect transistors:in a certain temperature range(290 K?380 K),when the temperature decreases,the gate capacitance is amplified,the potential amplification ability of silicon surface is enhanced,and the sub-threshold swing is reduced,thus the power consumption is reduced.The results are of great significance to the design of low power FET.(2)Based on the established SBT-MFS-NC-FET physical model,The influence of different silicon substrate doping concentration on the electrical properties of negative capacitance SBT ferroelectric field-effect transistor is analyzed.We have come to the following conclusions:in a certain doping concentration range(1017?1020/m3),when the doping concentration of silicon substrate is increased,there is no effect on the amplification factor,but the steep increase voltage is left shift and the sub threshold swing is reduced,thus the low power operation of the transistor is realized.(3)Based on the established SBT-MFS-NC-FET physical model,the influence of ferroelectric layer thickness on the electrical properties of negative capacitance SBT ferroelectric field-effect transistor is analyzed,we have come to the following conclusion:in a certain range of ferroelectric thickness(5-35 nm),the gate capacitance and the silicon surface potential can be amplified when increasing the thickness of ferroelectric layer.The subthreshold swing was decreased,this conclusions has certain reference value for optimizing the performance of negative capacitance FeFET.(4)Based on the established SBT-MFS-NC-FET physical model,we further consider a ferroelectric-electrode interface layer,analysis of the influence of interfacial layer thickness for the FeFET,we have come to the following conclusions:when the thickness of interface layer is reduced in a certain range,the amplification power of silicon surface potential increases,the sub-threshold swing becomes smaller,and the power consumption of transistor is reduced.This is of great significance to the design of a new ferroelectric field effect transistor with low power consumption.