Key Techniques Research And RFICs Design For SAW-less Anti-blocker Receiver Front-ends

With the rapid development of wireless communication technology in the past few decades,various wireless standards emerge endless.The current Sub-6GHz spectrum has become increasingly crowded with only a limited amount of unlicensed spectrum.Thus,making a single mobile terminal with multi-mode multi-standard?MMMS?becomes an important trend.Realizing the miniaturization,low power,reconfigurable and anti-blocker receiver is a huge challenge.This dissertation focuses on the research and design of MMMS SAW-less anti-blocker receiver front-ends.The main researches include RF front-end architecture of MMMS receiver,anti-blocker technology and reconfigurable method for receiver chain.This dissertation compares the advantages and disadvantages of various receiver structures and analyzes the source of interference signals in the SAW-less receivers.The state-of-the-art SAW-less MMMS receiver architectures are analyzed,and different anti-blocker design methods are summarized.This dissertation also summarizes the general calculation method of the receiver requirement,such as noise figure?NF?,linearity,and dynamic range.Link budget of the RF front-end was presented in detail according to the radio access files which the subject needs to be compatible.The bandwidth and gain of the RF front-end need to be reconfigurable for MMMS applications,which is a new challenge for the design.The reconfigurable RF bandpass filter?BPF?based on passive mixer is studied and a method of gain and bandwidth reconfiguration is proposed in this dissertation.A wideband reconfigurable anti-blocker RF front-end is implemented in TSMC 0.18?m RF CMOS process,which is consisted of a low noise amplifier?LNA?,a passive mixer and a test buffer.The front-end operates from 0.5 to2.5 GHz with measured maximum out-of-band rejection larger than 40 dB.The measured gain of voltage conversion(G_VC)of the front-end can be changed from 5 to 17 dB,the maximum input intercept point?IIP3?is 0 dBm and the minimum NF is 3.7 dB.And the base-band capacitor of the mixer can be variable to offer 15 kinds of intermediate frequency bandwidth.In order to further increase the linearity of the RF front-end for enhancing the capability of anti-blocker,this dissertation proposes a broadband current-mode front-end with high linearity.The advantages and disadvantages of voltage-mode and current-mode receiver architecture are analyzed and compared.And the main performances of current-mode front-end are analyzed in detail.A high linearity wideband current-mode front-end is design by adding an on-chip BPF at output of low noise transconductance amplifier?LNTA?,which can effectively improve the out-of-band rejection of the front-end.Meanwhile,the operational transconductance amplifier?OTA?uses a dual feedback compensation method to extend the-3dB bandwidth of OTA effectively in the transimpedance amplifier?TIA?.The proposed current-mode front-end is realized in TSMC 65 nm CMOS process,which is included a LNTA,an IQ quardure mixer,a BPF,a non-overlapping clocker,OTAs and TIAs.The measured results show that the front-end operates from 0.5 to 2.5 GHz with maximum G_VC of 33 dB,in-band IIP3 of-6.5 dBm,the maximum out-of-band IIP3 of 11.5 dBm and NF is 5 dB.In addition,based on the test conditions,the post simulation result shows that NF is less than 15 dB when the front-end encounters a-5 dBm blocker at 80 MHz offset.Thus,this front-end has high linearity and good anti-blocker ability.Finally,A SAW-less receiver front-end with an active adjustable feedback loop for blocker-filtering is implemented by using IBM 0.13?m BiCMOS process in this dissertation.By studying the RF BPF formed by the active feedback loop,a novel method of controlling bandwidth is proposed.And the bandwidth of BPF can be adjusted continuously to the desired value over a wide range.And a method for analyzing the linearity of bipolar transistor amplifiers is proposed,which provides theoretical guidance for the design of high linearity bipolar circuits.The front-end includes a reconfigurable LNA,reconfigurable OTAs,reconfigurable TIAs,reconfigurable loop capacitors and loop amplifiers which gain can be changed continuously.Thereby,the bandwidth of the entire RF front-end can be adjusted continuously and the gain is reconfigurable.The front-end operates from 0.1 to 2.5 GHz.The measured-3 dB IF bandwidth of the front-end can be easily reconfigured from 1 to 20 MHz continuously only using 46 pF capacitors and achieves maximal 38 dB of out-of-band rejection at 100 MHz offset frequency.Meanwhile the G_VC of front-end can also be reconfigured from 5 to 40 dB to fulfill requirements of linearity and noise performance of different received signals.The minimum NF is 6.3 dB,and the maximum in-band 1 dB compression point and IIP3 are 0.1 dBm and 10.7 dBm respectively,showing good out-of-band linearity.Moreover,with blocker-filtering enhanced by using auxiliary capacitors and the loop amplifier buffers,the front-end can resist-5-dBm blocker at 100 MHz offset.In this dissertation,in-depth research on the key technologies of MMMS SAW-less anti-blocker receiver front-ends from the system and module layers is conducted.A variety of anti-blocking,high linearity and broadband reconfigurable front-ends have been proposed.The measured results indicate that these three front-ends are the good candidates for MMMS SAW-less receivers.