Research On Concurrent Error Detection Technologies For Block Cipher Hardware

The concurrent error detection technique can detect the natural faults induced by the environment and the intentional faults that are used for fault attack,which makes it an important mean to ensure the reliability and security of the block cipher hardware.It has become a hot and difficult problem in the cross field of cryptography and integrated circuits to realize efficient error detection at a low cost.In this paper,the features of block cipher hardware faults are analyzed systematically,and then the design process of concurrent error detection scheme for cryptographic hardware is proposed.Serval low overhead concurrent error detection schemes are proposed for operation level,round operation level and processor architecture level block cipher hardware respectively.The main work and research results are as follows:The low overhead error detection scheme for different operations of block ciphers is analyzed.A multi-parity based error detection scheme is proposed for nonlinear operation S box,and a structural parameter calculation model of detection scheme is built.The structural parameter calculation model can determine the total number of predicted parities for error detection according to the expected fault coverage,which can guide the design of multi-parity based error detection scheme.Two multi-parity based fault detection schemes which divided the composite field S-box based on redundant GF arithmetic into multiple blocks were designed on the basis of that number calculated by the model.The simulation results show that the fault coverage rate of the two fault detection schemes is both about 97% for the random multiple faults and the fault coverage rates of the two schemes for the burst faults are 61.8% and 76.3%,respectively,which are better than most error detection schemes in existing works.In order to optimize the S-box circuit with fault detection capability,an enhanced delay aware common subexpression elimination algorithm is proposed.Under different delay constraints,the proposed algorithm can not only optimize multiple constant multiplication circuit,but also provide all of the design trade-offs,from the shortest feasible delay to the smallest area.Two constructions of S-box based on redundant finite field arithmetic which had optimal delay or the optimal area are derived using the algorithm.The results obtained through optimizing examples show the algorithm achieves high optimization efficiency.Experimental results show that compared with the existing delay aware subexpression elimination algorithm,the proposed algorithm has high optimization efficiency and and better overall delay optimization effect.Compared to the fault detection schemes with similar fault detection ability,the area-delay product of the designed circuit has been reduced by 7.02% compared with the existing S-box circuit with the best area-delay performance.A half round level invariance based concurrent error detection is proposed for round operation circuit which takes advantage of algorithm property.By decomposing AES round into two sub-blocks pipelined structure,the proposed scheme uses one sub-block for encryption and the other one for re-encryption at the same time to detect faults which can reduce performance overhead.Based on the proof of half round level invariance,the re-computing method with permuted operands is introduced into the process of half round encryption in order to detect permanent faults and resist double fault attack.Experimental results show that the fault coverage of the proposed scheme is 91.046% for the random single fault and 99.242% for the multi bit fault respectively.Compared with other concurrent error detection schemes with similar fault coverage,the proposed scheme has more reasonable area and throughput overhead.A redundant parallel computing performance cost model of block cipher processor is built,which provides theoretical guidance for designing low overhead concurrent error detection schemes.Under the guidance of the model,a low overhead concurrent error detection method based on instruction replication and software pipelining is proposed for reconfigurable block cipher stream processor.Through the architecture design to support efficient error detection,the approach that adopts the conception of hardware-software co-design achieves the compilerassisted instruction duplication with a vulnerability-aware duplication algorithms which can improve the fault detection ability of processor under performance constraints.Experimental results show the hardware overhead of the approach is only 1.5%.Compared to the counterparts in existing literatures,under the same performance overhead constraint,the random fault coverage rate of this method is slightly higher than that of previous methods,and the malicious fault coverage rate is significantly better than that of previous methods.The throughput overheads of typical cipher such as SP(AES-128),Feistel(SMS4),L-M(IDEA)is 25.6%,17.9%,15.7% respectively after complete code duplication using this method.The implementation of ciphers that supports error detection has the lowest performance cost and highest area energy efficiency ratio compared to the counterparts in existing literatures.