Research On GPU Power Estimation And Optimization Technology

The paper comes from the key project of the National Natural Science Foundation of China,"Research on the new generation of graphics processing system chip architecture and key technology".The application of GPU(Graphics Processing Unit)has been extended from the areas of desktop computing systems,handheld and portable electronic devices,game consoles and other fields to high-performance computing and artificial intelligence.The GPU architecture evolved from the original dedicated graphics accelerator to the current SIMD(Single Instruction Multiple Data)or SIMT(Single Instruction Multiple Threads)processor.A modern GPU is more than just a special use accelerator or geometry engine,it can also be used as a general-purpose computing chip.Under the drive of integrated circuit technology progress and application development,the current graphics processing system chip is undergoing changes.Therefore,aiming at the demand of new graphics algorithm and general-purpose computing,facing the continuous development of advanced application of GPUs in the future,we should deal with problems such as long lines,power consumption and process defects in terms of architecture.It is of great scientific significance to study the architecture and key technologies of the new generation of graphics system chips.Studying and designing GPU chips and breaking the monopoly of foreign countries are the urgent needs of our social and economic development.In this paper,we study the architecture design,power estimation and power optimization of a polymorphic parallel GPU.The main contributions of this dissertation are as follows:1.A hardware architecture of polymorphic parallel graphics processor is proposed.In order to better adapt to the requirements of new graphical computing and general computing,to meet the challenge of future chip manufacturing process,a polymorphic parallel GPU architecture is proposed.The chip is implemented as Firefly2.The architecture of Firefly2 is a two-dimensional array of homogeneous processor units,with adjacent interconnect technology between processors.Adjacent interconnect technology decreases the long lines,reduces power consumption,and facilitates signal integrity.The processor instruction set is optimized according to a large number of graphical processing simulation tests and statistical analysis results.The instruction system is designed to ensure the adjacency addressing of the instruction,and the program consisting of the neighbor addressable instruction can "reconstruct" the processor array,so that it can complete the operation level parallel computing as efficiently as the dedicated circuit.The same instructions can be executed by multiple processors through instruction broadcasting to complete the data level parallel computing.The instruction group(consisting of multiple instructions)stored in the instruction memory can perform thread-level parallel computation of the multiple instruction stream.In this way,various parallel computing modes are realized by using instruction stream computing,and the flexibility of program design and the efficiency of computation are achieved.In addition,we implemented 3D graphics rendering pipeline and computer vision applications on Firefly2 processor,and carried out simulation experiments.Experimental studies have shown that the Firefly2 architecture has the potential to perform graphics rendering and image processing programs with high performance.2.Correct and effective power modeling and evaluation techniques are the basis for effective low-power design.Without an accurate means of estimating power consumption,it is difficult to design a chip that meets the power budget.A new energy consumption estimation model for 3D graphics rendering pipeline is proposed in this paper,including the energy consumption estimation model of 3D graphics rendering stage,the energy consumption estimation model of data memory access and the energy consumption estimation model of instruction memory access.By analyzing the load of two key modules,vertex shader and pixel shader,which affect rendering quality in 3D rendering pipeline,the ratio model of pixel number to vertex number is obtained.At the same time,the energy consumption of 3D graphics rendering pipeline is modeled by forward analysis and the combination of classical graphics rendering algorithm,including geometric transformation stage,the vertex shading stage,frustum clipping stage,back-face culling stage,scan conversion stage,pixel shading stage and fragment operation stage.The energy consumption estimation model of vertex shading stage and pixel shading stage is verified.The results show that the model achieves high prediction accuracy.The difference from previous research is that the modeling process does not make any assumptions about the underlying hardware architecture,making the model a wide range of applicability.3.VLSI technology can integrate tens of billions of transistors into a single chip.The increase in integration density brings a huge enhancement in computing power of GPU,but also brought tremendous energy consumption.Power consumption has become the most critical factor in today's GPU design,and effective power structure design has become one of the important factors that determine the performance of GPU chips.Starting from the analysis of the source of power consumption,this paper analyzes the power consumption in the integrated circuit,and the low-power design technology that can be adopted at process level,circuit level,logic level,RTL level,architecture level and system level is studied.Some measures to reduce power consumption are proposed at the software level and the hardware level respectively,and the experimental verification is carried out.At the software level,several low power programming techniques suitable for 3D graphics rendering are put forward by theoretical analysis and simulation,including vertex sharing,clock switching technology(HALT command),LOD technology and static target caching technology(BEGIN_OBJ and END_OBJ commands).Experimental results show that these low power programming technologies can significantly reduce the power consumption and energy consumption of 3D graphics applications.At the hardware level,the main power optimization measures include multi-threshold technology,clock gating technology,power gating technology and multi voltage technology.The analysis results show that power consumption is reduced by 65.23% by adopting the above hardware-level power optimization technology.4.A design method of energy aware processing element(PE)scheduler is proposed.Firstly,we use Amdahl's law to model the power consumption and energy consumption of Firefly2 processor.Then,a minimized energy consumption scheduling algorithm that takes into account energy efficiency is proposed.Finally,based on the established power consumption model,energy consumption model and scheduling algorithm,and the use of the system designed performance counters,completed the PE scheduler design.The scheduling strategy of the designed PE scheduler is to select the running PEs and the work frequency of the PEs according to the application.