Studies On Key Techniques Of IP Watermarking In Integrated Circuits

With the continuous development of deep submicron integrated circuit system,people's demands for integrated system have been greatly improved.More and more logic functions are expected to be implemented on one silicon slice.Meanwhile,FPGA has gradually become mainstream technology in integrated circuit design.In development of FPGA-based designs,IP(Intellectual Property)reuse technology is adopted to shorten design cycle and reduce risk for designing products.Consequently,IP protection in reuse technology has become a key issue of common concerns for many semiconductor companies and research institutes.In this paper,our work concentrates on IP watermarking technology in integrated circuits.By studying on existing IP watermarking algorithms,the drawbacks of existing algorithms include performances of lower security,high resource overhead,bad traceability and lower watermark self-recovery.Aiming at these drawbacks,five IP watermarking algorithms have been proposed in fields of SOC(System on Chip)design,sequential logic circuits,FSM(Finite State Machine)design and DFT(Design for Test),etc.In other words,three watermark embedding algorithms,a blind watermark detection scheme and a watermark recovery scheme are proposed.All of the researches are stated briefly as follows:(1)A chaotic IP watermarking scheme at physical layout was proposed.This scheme has increased the flexibility of existing IP protection schemes.The watermarking overhead was also reduced.By considering features of LUT(Look-up Table)in FPGA,the scheme used chaotic mapping for dual encryption in watermark design and embedding procedure.The watermarks were scrambled by using chaotic sequence.Furthermore,two random sequences were generated with chaotic mapping.One sequence indicated LUT positions for embedding watermarks and another was used to determine number of watermark bits in each fragment.The experiments on Virtex XCV600-6bg432 FPGA show no interference on logic function of IP design.The algorithm has high security and low resource overhead.(2)An IP protection method was proposed on basis of timing redundant attributes in FSM.The existing FSM-based IP watermarking methods have drawbacks of high resource overhead and low security.By considering the stability of logic states in complex circuit,the algorithm use state transitions in STG(State Transition Graph)and extract the maximum timing states in logic function of circuit.The watermarks were inserted in timing states of circuit.Once the timing information of redundant logic states was attacked by power attacks,the IP owner needs to rebuild new redundant logic states with the transformation table of timing states,making the states not be attacked.The analysis and experiments show that our proposed method has good effectiveness for watermark embedding and extraction.Moreover,the performances on resource overhead and ability against attacks are encouraging.(3)An IP protection method based on multiple scan chains was proposed on basis of minimum correlation of vectors.The issue of correlation between multiple scan chains in existing architecture of multiple scan chains may lead to higher resource overhead and reliability of watermark embedding.Firstly,the test vector sequence for scan input is generated by the generator of pseudo-random test vector;then the multiple scan chains based watermarking structure with different correlation of vectors will be constructed by combining the generated sequence with the circuit-under-test.By adding constraints in the structure,watermark will be restricted to positions of certain scan cells.Finally,the watermark can be inserted or extracted by altering states of specific registers in scan cells with the designed logic circuit for bit alteration.The proposed algorithm has no influence on normal circuit function.The watermark indicated ownership could be effectively embedded and extracted.Meanwhile,the correlation of test vector is obviously reduced.Our algorithm has good performance on embedding overhead and the reliability is encouraging.(4)A blind IP watermark detection algorithm based on zero-knowledge proof was proposed for protecting ownership.The watermark embedding combines with zero-knowledge proof.It compensates for other schemes in which watermarks cannot be blindly detected on-site.The key threshold in watermark zero-knowledge protocol is used as evidence for secure authentication.Meanwhile,the key threshold and owner's identity information are public through method in zero-knowledge protocol.The scrambling algorithm is chosen for watermark scrambling in total and in group.In this case,watermark detection in public will be secure.Finally,watermarks can be blindly authenticated even without original IP cores.The credibility in public watermark detection has enhanced.The experiments show that the scheme has good stability and security.(5)An IP watermarking scheme based on self-recovery of secret information was proposed.The scheme considered the extent of impaired watermark after suffering attacks.In watermark preprocessing,special expression was used to compress number of watermarks.After that the watermarks were embedded into index table as redundant attributes identifier of unused LUTs.The experiments show that the watermarks can be restored even the impaired parts reached 40%under illegal attacks.Different with watermarking schemes,the proposed scheme has good ability against removal attacks.Besides,it performs well in performances of watermark number and self-recovery.In conclusion,this work has considered the application requirements of IP watermark technology.The necessity and feasibility of IP protection mechanisms was analyzed.In fields of cryptology and information hiding,five types of IP watermarking schemes has been proposed by considering different constraints.An effective prototype system was developed on basis of real application environment in IP trading.Our work has lay good theoretical foundation for development of IP protection technology.Furthermore,it plays an active role in promoting application of IP protection technology in integrated circuits.