Research On Low Soft Error Phase Locked Loop For Serdes

With the progress of China's space industry and the rapid development of space-based Internet,massive data leads to the urgent need to improve the signal processing capacity of on-board systems.The signal processing capability of on-board systems is determined by processor performance and inter-chip communication capability.Because PLL provides high frequency jitter clock signals for core chips such as processors and SerDes,PLL becomes a key subsystem limiting the signal processing capability of on-board systems.PLL for SerDes applications has higher requirements for frequency,jitter and other indicators,so it is urgent to break through this key technology.As process sizes have shrunk,SET has become a major source of soft errors for PLL.In order to maintain PLL stable operation and low soft error rate,anti-set hardening design must be carried out for PLL.This paper comprehensively discusses the existing general SET hardening technology and PLL SET hardening technology,analyzes the limitations of the current hardening technology,and concludes that the traditional SET hardening design will cause the performance degradation of important indicators such as frequency and jitter,and the direct use of the existing hardening technology will lead to the failure of the PLL after hardening to meet the performance requirements of SerDes.It is necessary to propose a new hardening method to ensure that PLL frequency,jitter and other performance indicators will not decline.In this paper,low-soft error PLL technology for SerDes was studied.Based on a non-reinforced high-performance PLL,the SET sensitive areas of different sub-modules of the non-reinforced high-performance PLL were analyzed through laser experiments.Based on the sensitivity of the sub-modules,the hardening and transformation of the non-reinforced high-performance PLL SET were implemented to reduce the soft errors of the PLL SET.This paper studies the corresponding hardening method from two levels of PLL system-level hardening technology and PLL module-level hardening technology,so as to solve the damage of existing hardening technology to PLL performance.The main contents and innovations of this paper are as follows:(1)design a non-reinforced high-performance self-biased PLL.The chip test results show that the PLL output clock signal Rj jitter is less than 3ps,Dj jitter is 5ps,can provide SerDes with the highest 3.125Ghz multi-phase low-jitter clock signal.This PLL plays a technical support role for the follow-up research on PLL reinforcement with low soft fault.Through the laser experiment,the SET sensitivity of different submodules can be qualitatively determined,providing a research basis for the subsequent reinforcement.(2)the double-ring self-sampling system-level reinforcement technology is proposed to reinforce PLL.The double-loop self-sampling reinforcement technology does not make specific restrictions on the PLL structure.Double backup is made for the PLL feedback loop,and the SET occurring in the PLL feedback loop is filtered by using the phase dead zone in the PFD.Redundant transistor layout strengthening technology was adopted to improve the anti-radiation ability of the sampler.Laser experiment proved that this strengthening technology raised the threshold of this part from 500pJ to1400pJ,effectively improving the anti-set performance of PLL feedback loop.(3)the sensitive node transfer method and multi-channel discharge technology are proposed to reinforce the charge pump.The most sensitive nodes are converted into relatively insensitive areas to solve the sensitivity problem of charge pump switching circuit.The mismatch performance of the pump is improved by increasing the voltage amplitude of the power supply.A multi-channel discharge technique is proposed to improve the anti-SET performance of bias circuit.According to the simulation results,the charge pump will cause PLL unlocking before reinforcement,and only cause PLL output frequency fluctuation of 500MHz after reinforcement.The voltage fluctuation of the unstrengthened bias circuit is 1.17v and 0.37v respectively,while the voltage fluctuation of the strengthened bias circuit is 0.048v and 0.046v,and the maximum inhibitory effect of the voltage variation after the reinforcement is about 94%.(4)propose multi-offset technology and cross-coupling technology to reinforce VCO's offset circuit and ring vibration respectively.The reinforced VCO can satisfy high frequency,multi-phase and low noise.Multi-offset technology solves the impact of SET generated by offset part on VCO,and cross-coupling technology solves the sensitivity of VCO ring vibration to SET.The above two reinforcement methods will not damage the original VCO structure,but only increase the VCO area and power consumption,and will not cause the attenuation of noise,frequency and other indicators.Heavy ion experiments showed that multi-offset VCO still did not SET at LET value of83.7MeV cm~2/mg.The laser experiment shows that the laser threshold increases from1.4nj to 3.5nj,and the experiment proves that the multi-bias technology can effectively improve the anti-set performance of VCO.The cross-coupling technology solves the sensitivity of the VCO ring vibration part to SET.The circuit simulation shows that the unreinforced VCO generates a frequency change of 2.7Ghz under SET bombardment,and the cross-coupled VCO after reinforcement generates a frequency change of0.47ghz under SET bombardment,which proves that the reinforcement effect of the VCO is significantly improved.(5)put forward the technology of internal circulation force update frequency divider.An update mechanism is designed to change the wrong value into the correct value,and the voting device is inserted into the feedback loop of the frequency divider,which solves the problem of SEU accumulation in the traditional TMR frequency divider.This method does not need to increase additional area or power consumption,and will not destroy the original structure of the divider,will not cause the performance of the divider significantly reduced.The heavy ion experiment shows that the SET/SEU still does not occur when the frequency divider LET is 83.7MeV cm~2/mg.The laser experiment shows that the laser threshold also rises from 1150pJ to 2400pJ,and the experiment proves that the above reinforcement technology can effectively improve the anti-set performance of the frequency divider.