Research And Design Of Low-voltage Trench-gate Mos Devices With High Cell Density

Trench-gate MOSFET,as an typical representative of power MOSFET,has the advantages of huge power density,fast switching speed and low driving consumption and used as high-speed switches to complete the mutual conversion of various forms of electrical energy.High conversion efficiency requires devices to have lower losses and under the development trend of chip miniaturization,reducing device size and increasing cell density are effective solutions.Therefore,how to realize trench-gate MOS device structure with high cell density under a certain lithography size has become a research hotspot.Based on domestic 8-inch wafer production line,the topic of this project focuses on two low-loss trench-gate MOS devices with high cell density,one is ONO SGT MOSFET with ONO(Oxide-Si N-Oxide)structure in the trench,the other is NM Trench MOSFET with Narrow-MESA(NM)region design.The main work content are as follows:For ONO SGT MOSFET,its structural characteristics are firstly described,and the reason for introducing Si N into trench is introduced.With the assistance of the Si N layer,the influence of the thermal oxidation that is used to grow isolation oxide layer on the trench morphology in the traditional process can be isolated so that the cell pitch can be reduced from 1.2?m of traditional SGT MOSFET to 0.8?m of ONO SGT MOSFET under the same production capacity.Then,its working mechanism is analyzed and the manufacturing process of the device is introduced and the isolation effect of the Si N layer can be seen intuitively.Through the TCAD simulation,30 V level device is simulated and the influence of various structural parameters and process parameters of the device on the device performance are analyzed so that the optimal selection of each parameter of device cell is obtained and breakdown voltage of 35 V and specific on-resistance of 5.63 m?·mm~2 are achieved.According to the experimental purpose and design considerations,the layout structure of the device is studied and designed in detail including the cell area,terminal area,gate extraction design,etc.Combined with present experimental conditions,a reasonable tape-out plan is formulated and the tape-out experiment is successfully carried out.For NM Trench MOSFET,its structural characteristics and working mechanism are expounded.The extraction of the P-type well region is realized by three-dimensional P plus region so that the metal holes between trenches are removed and the width of the MESA region is greatly reduced.The manufacturing process is introduced,and the key structural parameters of device cell with 20 V breakdown voltage are simulated so that the parameter selection of the length of the P plus region of 1.0?m and its proportion to the length of the cell region of 10%is obtained.After successful tape-out,the breakdown voltage of 24 V and specific on-resistance of 4.88 m?·mm~2 are obtained,and the failure phenomena of drain-source breakdown voltage caused by Al diffusion was analyzed.Based on that,the failure mechanism of double diffusion between metal aluminum and silicon is proposed,and the corresponding failure model is established.Group experiments are carried out to verify the correctness of the model,and the solution is proposed that removing titanium in the metal barrier layer and requiring the total thickness of titanium nitride to be greater than 30 nm,which provides a reference for manufacturing process improvement in the subsequent mass production stage.