| Multiphase interleaved DCDC converter technology in recent years becomes a hot spot of switching power supply module, thanks to its interleaved phase branch circuit control, easy to realize with digital means, the frequency doubling characteristics of equivalent topology to have fast transient response ability, and very low output voltage ripple and efficiency across the full load range. At present, there is no high current multi-phase DCDC converter chip design capability in land, the power chip using for multi-core processors relies on European and American overseas enterprises. This paper relies on the major national project "based on domestic advanced technology platform for mobile terminal chip design and industrialization".As power supplies for the advanced SOC baseband processor of mobile terminal, high current multiphase interleaved DCDC converter chip has been researched and designed, broken the technical gaps of this kind of chips in China.In this paper, starting from the limitations of the traditional single-phase buck converter, a detailed comparison of the current control technology based on multi-phase expansion strategy, obtained based on different control modes multiphase topology design feasibility and disadvantages. Creatively from the point of the phase interference between branches phases, the paper has theoretically completed multiphase interleaved BUCK steady relationship equivalent output voltage ripple and the number of phases and duty cycle. As an innovation, the paper deduced the function relationship between the transient response of the multi-phase BUCK large signal and the component parameters and the circuit parameters. And put forward the optimization design method for the efficiency of the multiphase BUCK.Based on the theoretical analysis and formula guide, it is applied to the design of a multi-core CPU and GPU power supply BUCK converter for a smart phone. From application requirement, system definition to the operation mode switch of different load stage, including all phase PWM mode in heavy load, light load PFM and low power mode, and multiphase buck important module design, covering interleaved the design and simulation of, such as, clock generating circuit, current sampling and banlance, double loop small signal analysis and main amplifier, a phase number automatically adjust at different load, the remote differential feedback circuit analysis and so on. There is an innovation point, which is the use of the current sampling technology through both high side and low side powerMOS element, to overcome the speed problem using high side sampling method at extremely low duty cycle. Further,the originality of this paper put forward the phase number of automatic switching strategy, without introducing the average current sampling resistance and additional sampling pin, and has completed an academic paper and a domestic patent applicationsubmitted.The circuit’s layout, the ESD consideration, and other device reliability challenges frequently encountered in switching power supply design are also described in this paper. There are also some focuses on recording and analyzing the data of post-simulation of the whole circuit, used to evaluate the key performance of multiphase BUCK. The chip has been taped out in 0.18um process and package with wafer level CSP (WCSP), whose area is 3.2 * 3.2mm2,each path with output 6A current capacity, the programmable output voltage from 0.65V to 1.4V. supports inductors low as 330nH of small package, according to the load phases auto selection of 1-3 branches, and PFM mode at light load or low power mode. Measured results show that key performances are not lower than the level of foreign commercial competitor’s chips, 80% efficiency within 4A, the output ripple is less than 10mV, the transient voltage change is less than 50mV in 3A/us transient load. It should be a good example or reference design for other similar field studies. |
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